Datasheet

TWCRn must hold a value of the type TWCRn=0100010x - TWCRn.TWEN must be written to '1' to
enable the TWI. TWCRn.TWEA bit must be written to '1' to enable the acknowledgment of the device’s
own slave address or the general call address. TWCRn.TWSTA and TWSTO must be written to zero.
When TWARn and TWCRn have been initialized, the TWI waits until it is addressed by its own slave
address (or the general call address, if enabled) followed by the data direction bit. If the direction bit is '0'
(write), the TWI will operate in SR mode, otherwise, ST mode is entered. After its own slave address and
the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR.
The status code is used to determine the appropriate software action, as detailed in the table below. The
SR mode may be entered if arbitration is lost while the TWI is in the Master mode (see states 0x68 and
0x78).
If the TWCRn.TWEA bit is reset during a transfer, the TWI will return a "Not Acknowledge" ('1') to SDA
after the next received data byte. This can be used to indicate that the slave is not able to receive any
more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the
two-wire serial bus is still monitored and address recognition may resume at any time by setting TWEA.
This implies that the TWEA bit may be used to temporarily isolate the TWI from the two-wire serial bus.
In all sleep modes other than the Idle mode, the clock system to the TWI is turned off. If the TWEA bit is
set, the interface can still acknowledge its own slave address or the general call address by using the
two-wire serial bus clock as a clock source. The part will then wake up from sleep and the TWI will hold
the SCL clock low during the wake-up and until the TWINT flag is cleared (by writing '1' to it). Further data
reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is
set up with a long start-up time, the SCL line may be held low for a long time, blocking other data
transmissions.
Note: The two-wire Serial Interface Data Register (TWDRn) does not reflect the last byte present on the
bus when waking up from these Sleep modes.
Table 26-6. Status Codes for Slave Receiver Mode
Status Code
(TWSR)
Prescaler
Bits are 0
Status of the Two-Wire Serial
Bus and Two-Wire Serial
Interface Hardware
Application SofTWARne Response Next Action Taken by TWI
Hardware
To/from
TWDRn
To TWCRn
STA STO TWINT TWEA
0x60 Own SLA+W has been
received;
ACK has been returned
No TWDRn
action
X 0 1 0 Data byte will be received and
NOT ACK will be returned
X 0 1 1 Data byte will be received and
ACK will be returned
0x68 Arbitration lost in SLA+R/W as
Master;
own SLA+W has been
received;
ACK has been returned
No TWDRn
action
X 0 1 0 Data byte will be received and
NOT ACK will be returned
X 0 1 1 Data byte will be received and
ACK will be returned
0x70 General call address has been
received;
ACK has been returned
No TWDRn
action
X 0 1 0 Data byte will be received and
NOT ACK will be returned
X 0 1 1 Data byte will be received and
ACK will be returned
0x78 Arbitration lost in SLA+R/W as
Master;
No TWDRn
action
X 0 1 0 Data byte will be received and
NOT ACK will be returned
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 295