Datasheet

Figure 26-15. Data Transfer in Slave Transmitter Mode
Device 3
Device n
SDA
SCL
........
R1 R2
V
CC
Device 2
MASTER
RECEIVER
Device 1
SLA VE
TRANSMITTER
To initiate the SR mode, the TWI (Slave) Address Register (TWARn) and the TWI Control Register
(TWCRn) must be initialized as follows:
The upper seven bits of TWARn are the address to which the two-wire serial interface will respond when
addressed by a master (TWARn.TWA[6:0]). If the LSB of TWARn is written to TWARn.TWGCI=1, the TWI
will respond to the general call address (0x00), otherwise, it will ignore the general call address.
TWCRn must hold a value of the type TWCRn=0100010x - TWEN must be written to one to enable the
TWI. The TWEA bit must be written to one to enable the acknowledgment of the device’s own slave
address or the general call address. TWSTA and TWSTO must be written to zero.
When TWARn and TWCRn have been initialized, the TWI waits until it is addressed by its own slave
address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “1”
(read), the TWI will operate in ST mode, otherwise, SR mode is entered. After its own slave address and
the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSRb.
The status code is used to determine the appropriate sofTWARne action. The appropriate action to be
taken for each status code is detailed in the table below. The ST mode may also be entered if arbitration
is lost while the TWI is in the Master mode (see state 0xB0).
If the TWCRn.TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the
transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the master receiver transmits a
NACK or ACK after the final byte. The TWI is switched to the not addressed Slave mode and will ignore
the master if it continues the transfer. Thus the master receiver receives all '1' as serial data. State 0xC8
is entered if the master demands additional data bytes (by transmitting ACK), even though the slave has
transmitted the last byte (TWEA zero and expecting NACK from the master).
While TWCRn.TWEA is zero, the TWI does not respond to its own slave address. However, the two-wire
serial bus is still monitored and address recognition may resume at any time by setting TWEA. This
implies that the TWEA bit may be used to temporarily isolate the TWI from the two-wire serial bus.
In all sleep modes other than the Idle mode, the clock system to the TWI is turned off. If the TWEA bit is
set, the interface can still acknowledge its own slave address or the general call address by using the
two-wire serial bus clock as a clock source. The part will then wake up from sleep and the TWI will hold
the SCL clock will low during the wake-up and until the TWINT Flag is cleared (by writing '1' to it). Further
data transmission will be carried out as normal, with the AVR clocks running as normal. Observe that if
the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other
data transmissions.
ATmega48PA/88PA/168PA
Two-Wire Serial Interface (TWI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 291