Datasheet
an interrupt is requested. The slave may continue to place new data to be sent to SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer register for later use.
Figure 23-2. SPI Master-Slave Interconnection
SHIFT
ENABLE
The system is single buffered in the transmit direction and double buffered in the receive direction. This
means that bytes to be transmitted cannot be written to the SPI Data register before the entire shift cycle
is completed. When receiving data, however, a received character must be read from the SPI Data
register before the next character has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct
sampling of the clock signal, the minimum low and high periods should be longer than two CPU clock
cycles.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to the table below. For more details on automatic port overrides, refer to the I/O Ports
description.
Table 23-1. SPI Pin Overrides
Pin Direction, Master SPI Direction, Slave SPI
MOSI User Defined Input
MISO Input User Defined
SCK User Defined Input
SS User Defined Input
Note: 1. See the I/O Ports description for how to define the SPI pin directions.
The following code examples show how to initialize the SPI as a master and how to perform a simple
transmission. DDR_SPI in the examples must be replaced by the actual Data Direction register controlling
the SPI pins. DD_MOSI, DD_MISO, and DD_SCK must be replaced by the actual data direction bits for
these pins, for example, if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with
DDRB.
Assembly Code Example
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi r17,(1<<DD_MOSI)|(1<<DD_SCK)
out DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out SPCR,r17
ATmega48PA/88PA/168PA
Serial Peripheral Interface (SPI)
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 229