Datasheet

illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and
TCNT2.
Figure 22-6. Fast PWM Mode, Timing Diagram
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
1
Period
2 3
OCnx
OCnx
(COMnx[1:0] = 0x2)
(COMnx[1:0] = 0x3)
OCRnx Interrupt Flag Set
4 5 6 7
The Timer/Counter Overflow flag (TOV2) is set each time the counter reaches TOP. If the interrupt is
enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the
COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated
by setting the COM2x[1:0] to three. TOP is defined as 0xFF when WGM2[2:0] = 0x3, and OCR2A when
MGM2[2:0] = 0x7. The actual OC2x value will only be visible on the port pin if the data direction for the
port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2x register at
the compare match between OCR2x and TCNT2, and clearing (or setting) the OC2x register at the timer
clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:

OCnxPWM
=

clk_I/O
  256
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A register represent special cases when generating a PWM waveform
output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for
each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low
output (depending on the polarity of the output set by the COM2A[1:0] bits).
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x
to toggle its logical level on each compare match (COM2x[1:0] = 1). The waveform generated will have a
maximum frequency of f
oc2
= f
clk_I/O
/2 when OCR2A is set to zero. This feature is similar to the OC2A
toggle in CTC mode, except the double buffer feature of the output compare unit is enabled in the fast
PWM mode.
ATmega48PA/88PA/168PA
8-bit Timer/Counter2 (TC2) with PWM and A...
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Datasheet Complete
DS40002011A-page 207