Datasheet

20.15.8 Timer/Counter 1 Interrupt Mask Register

Name: TIMSK1

Offset: 0x6F

Reset: 0x00

Property: -

Bit 7 6 5 4 3 2 1 0

ICIE1 OCIE1B OCIE1A TOIE1

Access

R/W R/W R/W R/W

Reset 0 0 0 0

Bit 5 – ICIE1 Timer/Counter 1, Input Capture Interrupt Enable

When this bit is written to '1', and the I-flag in the Status register is set (interrupts globally enabled), the

timer/counter 1 input capture interrupt is enabled. The corresponding interrupt vector is executed when

the ICF1 flag, located in TIFR1, is set.

Bit 2 – OCIE1B Timer/Counter 1, Output Compare B Match Interrupt Enable

When this bit is written to '1', and the I-flag in the Status register is set (interrupts globally enabled), the

timer/counter 1 output compare B match interrupt is enabled. The corresponding interrupt vector is

executed when the OCF1B flag, located in TIFR1, is set.

Bit 1 – OCIE1A Timer/Counter 1, Output Compare A Match Interrupt Enable

When this bit is written to '1', and the I-flag in the Status register is set (interrupts globally enabled), the

timer/counter 1 output compare A match interrupt is enabled. The corresponding interrupt vector is

executed when the OCF1A flag, located in TIFR1, is set.

Bit 0 – TOIE1 Timer/Counter 1, Overflow Interrupt Enable

When this bit is written to '1', and the I-flag in the Status register is set (interrupts globally enabled), the

timer/counter 1 overflow interrupt is enabled. The corresponding interrupt vector is executed when the

TOV1 flag, located in TIFR1, is set.

ATmega48PA/88PA/168PA

16-bit Timer/Counter1 (TC1) with PWM

Datasheet Complete

DS40002011A-page 193