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the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can
trigger a capture. The input capture flag must, therefore, be cleared after the change.
Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using
the same technique as for the T1 pin. The edge detector is identical. However, when the noise canceler is
enabled, additional logic is inserted before the edge detector, which increases the delay by four system
clock cycles. The input of the noise canceler and edge detector is always enabled unless the Timer/
Counter is set in a Waveform Generation mode that uses ICR1 to define TOP.
An input capture can be triggered by software by controlling the port of the ICP1 pin.
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20.13 Timer/Counter 0, 1 Prescalers
20.9.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise
canceler input is monitored over four samples, and all four must be equal for changing the output that in
turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler bit in the Timer/Counter
Control Register B (TCCR1B.ICNC). When enabled, the noise canceler introduces an additional delay of
four system clock cycles between a change applied to the input and the update of the ICR1 Register. The
noise canceler uses the system clock and is therefore not affected by the prescaler.
20.9.3 Using the Input Capture Unit
The main challenge when using the input capture unit is to assign enough processor capacity for handling
the incoming events. The time between two events is critical. If the processor has not read the captured
value in the ICR1 before the next event occurs, the ICR1 will be overwritten with a new value. In this case
the result of the capture will be incorrect.
When using the input capture interrupt, the ICR1 should be read as early in the interrupt handler routine
as possible. Even though the input capture interrupt has relatively high priority, the maximum interrupt
response time is dependent on the maximum number of clock cycles it takes to handle any of the other
interrupt requests.
Using the input capture unit in any mode of operation when the TOP value (resolution) is actively
changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each
capture. Changing the edge sensing must be done as early as possible after the ICR1 has been read.
After a change of the edge, the ICF must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICF is not required (if an interrupt handler is
used).
20.10 Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If
TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag
(TIFR1.OCFx) at the next timer clock cycle. If enabled (TIMSK1.OCIEx = 1), the output compare flag
generates an output compare interrupt. The OCFx is automatically cleared when the interrupt is
executed. Alternatively, the OCFx can be cleared by software by writing a logical one to its I/O bit
location. The waveform generator uses the match signal to generate an output according to operating
mode set by the Waveform Generation mode (WGM1[3:0]) bits and Compare Output mode (COM1x[1:0])
ATmega48PA/88PA/168PA
16-bit Timer/Counter1 (TC1) with PWM
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Datasheet Complete
DS40002011A-page 169