Datasheet

The table below shows the COM0A[1:0] bit functionality when the WGM0[2:0] bits are set to phase
correct PWM mode.
Table 19-5. Compare Output Mode, Phase Correct PWM Mode
(1)
COM0A[1] COM0A[0] Description
0 0 Normal port operation, OC0A disconnected.
0 1 WGM0[2:0]: Normal port operation, OC0A disconnected.
WGM0[2:1]: Toggle OC0A on compare match.
1 0 Clear OC0A on compare match when up-counting. Set OC0A on compare
match when down-counting.
1 1 Set OC0A on compare match when up-counting. Clear OC0A on compare
match when down-counting.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A[1] is set. In this case, the compare
match is ignored, but the set or clear is done at TOP. Refer to 19.7.4 Phase Correct PWM Mode for
details.
Bits 5:4 – COM0B[1:0] Compare Output Mode for Channel B
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B[1:0] bits are
set, the OC0B output overrides the normal port functionality of the I/O pin it is connected to. However,
note that the Data Direction Register (DDR) bit corresponding to the OC0B pin must be set in order to
enable the output driver.
When OC0B is connected to the pin, the function of the COM0B[1:0] bits depends on the WGM0[2:0] bit
setting. The table shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to a normal or
CTC mode (non- PWM).
Table 19-6. Compare Output Mode, Non-PWM
COM0B[1] COM0B[0] Description
0 0 Normal port operation, OC0B disconnected.
0 1 Toggle OC0B on compare match.
1 0 Clear OC0B on compare match.
1 1 Set OC0B on compare match.
The table below shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM
mode.
Table 19-7. Compare Output Mode, Fast PWM
(1)
COM0B[1] COM0B[0] Description
0 0 Normal port operation, OC0B disconnected.
0 1 Reserved.
ATmega48PA/88PA/168PA
8-bit Timer/Counter0 (TC0) with PWM
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40002011A-page 151