Datasheet

19.7 Modes of Operation

The mode of operation determines the behavior of the timer/counter and the output compare pins. It is

defined by the combination of the Waveform Generation mode bits and Compare Output mode

(TCCR0A.WGM0[2:0]) bits in the Timer/Counter Control Registers A and B (TCCR0A.COM0x[1:0]). The

Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode

bits do. The COM0x[1:0] bits control whether the PWM output generated should be inverted or not

(inverted or non-inverted PWM). For non-PWM modes, the COM0x[1:0] bits control whether the output

should be set, cleared, or toggled at a compare match (see the previous section Compare Match Output

Unit).

For detailed timing information refer to the following section Timer/Counter Timing Diagrams.

Related Links

22.6 Compare Match Output Unit

19.8 Timer/Counter Timing Diagrams

19.7.1 Normal Mode

The simplest mode of operation is the Normal mode (WGM0[2:0] = 0x0). In this mode, the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply overruns

when it passes its maximum 8-bit value (TOP=0xFF) and then restarts from the bottom (0x00). In Normal

mode operation, the Timer/Counter Overflow flag (TOV0) will be set in the same clock cycle in which the

TCNT0 becomes zero. In this case, the TOV0 flag behaves like a ninth bit, except that it is only set, not

cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 flag, the

timer resolution can be increased by software. There are no special cases to consider in the Normal

mode, a new counter value can be written any time.

The output compare unit can be used to generate interrupts at some given time. Using the output

compare to generate waveforms in Normal mode is not recommended since this will occupy too much of

the CPU time.

19.7.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare (CTC) mode (WGM0[2:0]=0x2), the OCR0A register is used to manipulate the

counter resolution: the counter is cleared to ZERO when the counter value (TCNT0) matches the

OCR0A. The OCR0A defines the top value for the counter, hence its resolution. This mode allows greater

control of the compare match output frequency. It also simplifies the counting of external events.

The timing diagram for the CTC mode is shown below. The counter value (TCNT0) increases until a

compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.

Figure 19-5. CTC Mode, Timing Diagram

ATmega48PA/88PA/168PA

8-bit Timer/Counter0 (TC0) with PWM

Datasheet Complete

DS40002011A-page 143