Datasheet

36
8025M–AVR–6/11
ATmega48P/88P/168P
When applying an external clock, it is required to avoid sudden changes in the applied clock fre-
quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is
required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page
36 for details.
9.9 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
9.10 Timer/Counter Oscillator
ATmega48P/88P/168P uses the same crystal oscillator for Low-frequency Oscillator and
Timer/Counter Oscillator. See ”Low Frequency Crystal Oscillator” on page 33 for details on the
oscillator and crystal requirements.
ATmega48P/88P/168P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with
XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four
times the oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can
only be used when the Calibrated Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See ”Asynchronous Operation of Timer/Counter2” on page 153 for further
description on selecting external clock as input instead of a 32.768 kHz watch crystal.
9.11 System Clock Prescaler
The ATmega48P/88P/168P has a system clock prescaler, and the system clock can be divided
by setting the ”CLKPR – Clock Prescale Register” on page 387. This feature can be used to
decrease the system clock frequency and the power consumption when the requirement for pro-
cessing power is low. This can be used with all clock source options, and it will affect the clock
frequency of the CPU and all synchronous peripherals. clk
I/O
, clk
ADC
, clk
CPU
, and clk
FLASH
are
divided by a factor as shown in Table 29-3 on page 314.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
Table 9-16. Start-up Times for the External Clock Selection
Power Conditions
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset (V
CC
= 5.0V) SUT[1:0]
BOD enabled 6 CK 14CK 00
Fast rising power 6 CK 14CK + 4.1 ms 01
Slowly rising power 6 CK 14CK + 65 ms 10
Reserved 11