Features • High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • • – 131 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments – 4/8/16KBytes of In-System Self-Programmable Flash progam memory – 256/512/512Bytes EEPROM – 512/1K/1KBytes Internal SRAM – Write/Erase Cycles:
1. Pin Configurations Figure 1-1.
ATmega48P/88P/168P 1.1 1.1.1 Pin Descriptions VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 86. 1.1.7 AVCC AVCC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6:4 use digital supply voltage, VCC. 1.1.8 AREF AREF is the analog reference pin for the A/D Converter. 1.1.
ATmega48P/88P/168P Block Diagram Block Diagram GND Figure 2-1. VCC 2.1 Watchdog Timer Watchdog Oscillator Oscillator Circuits / Clock Generation Power Supervision POR / BOD & RESET debugWIRE Flash SRAM PROGRAM LOGIC CPU EEPROM AVCC AREF DATABUS GND 8bit T/C 0 16bit T/C 1 A/D Conv. 8bit T/C 2 Analog Comp. Internal Bandgap USART 0 SPI TWI PORT D (8) PORT B (8) PORT C (7) 2 6 RESET XTAL[1..2] PD[0..7] PB[0..7] PC[0..6] ADC[6..
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega48P/88P/168P 2.2 Comparison Between ATmega48P, ATmega88P and ATmega168P The ATmega48P, ATmega88P and ATmega168P differ only in memory sizes, boot loader support, and interrupt vector sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the three devices. Table 2-1.
3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device.
ATmega48P/88P/168P 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1.
ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
ATmega48P/88P/168P specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.3.
7.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega48P/88P/168P 7.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3.
7.5.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Register Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND Read/Write Initial Value 7.
ATmega48P/88P/168P 7.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<
ATmega48P/88P/168P 8. AVR Memories 8.1 Overview This section describes the different memories in the ATmega48P/88P/168P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega48P/88P/168P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.2 In-System Reprogrammable Flash Program Memory The ATmega48P/88P/168P contains 4/8/16 bytes On-chip In-System Reprogrammable Flash memory for program storage.
Figure 8-1. Program Memory Map, ATmega48P Program Memory 0x0000 Application Flash Section 0x7FF Figure 8-2.
ATmega48P/88P/168P 8.3 SRAM Data Memory Figure 8-3 shows how the ATmega48P/88P/168P SRAM Memory is organized. The ATmega48P/88P/168P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
8.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 8-4. Figure 8-4. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 8.4 Next Instruction EEPROM Data Memory The ATmega48P/88P/168P contains 256/512/512 bytes of data EEPROM memory.
ATmega48P/88P/168P 8.4.2 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
8.6 8.6.1 Register Description EEARH and EEARL – The EEPROM Address Register Bit 15 14 13 12 11 10 9 8 0x22 (0x42) – – – – – – – EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 Read/Write Initial Value R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15:9 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero.
ATmega48P/88P/168P is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 8-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Operation Reserved for future use • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read.
ATmega48P/88P/168P Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega48P/88P/168P 9. System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 40. The clock systems are detailed below. Figure 9-1.
9.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 9.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
ATmega48P/88P/168P selectable delays are shown in Table 9-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical Characteristics” on page 322. Table 9-2. Number of Watchdog Oscillator Cycles Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles 0 ms 0 ms 0 4.1 ms 4.3 ms 512 65 ms 69 ms 8K (8,192) Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC.
Figure 9-2. Crystal Oscillator Connections C2 XTAL2 (TOSC2) C1 XTAL1 (TOSC1) GND The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL[3:1] as shown in Table 9-3 on page 30. Table 9-3. Low Power Crystal Oscillator Operating Modes(3) Frequency Range(1) (MHz) Recommended Range for Capacitors C1 and C2 (pF) CKSEL[3:1] 0.4 - 0.9 – 100(2) 0.9 - 3.0 12 - 22 101 3.0 - 8.0 12 - 22 110 8.
ATmega48P/88P/168P Table 9-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued) Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT[1:0] Crystal Oscillator, BOD enabled 16K CK 14CK 1 01 Crystal Oscillator, fast rising power 16K CK 14CK + 4.1 ms 1 10 Crystal Oscillator, slowly rising power 16K CK 14CK + 65 ms 1 11 Oscillator Source / Power Conditions Notes: 9.4 1.
Figure 9-3. Crystal Oscillator Connections C2 XTAL2 (TOSC2) C1 XTAL1 (TOSC1) GND Table 9-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT[1:0] Ceramic resonator, fast rising power 258 CK 14CK + 4.
ATmega48P/88P/168P 9.5 Low Frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega48P/88P/168P oscillator is optimized for very low power consumption, and thus when selecting crystals, see Table 9-7 on page 33 for maximum ESR recommendations on 6.5 pF, 9.
Table 9-10. CKSEL[3:0] Start-up Time from Power-down and Power-save 0100(1) 1K CK 0101 32K CK Note: 9.6 Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Recommended Usage Stable frequency at start-up 1. This option should only be used if frequency stability at start-up is not important for the application Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock.
ATmega48P/88P/168P 9.7 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL Fuses to “11” as shown in Table 9-13. Table 9-13. Note: 128 kHz Internal Oscillator Operating Modes Nominal Frequency(1) CKSEL[3:0] 128 kHz 0011 1. Note that the 128 kHz oscillator is a very low power clock source, and is not designed for a high accuracy.
Table 9-16. Start-up Times for the External Clock Selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) SUT[1:0] BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms 10 Power Conditions Reserved 11 When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU.
ATmega48P/88P/168P neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted.
9.12 9.12.1 Register Description OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
ATmega48P/88P/168P The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting.
10. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes. See ”BOD Disable” on page 41 for more details. 10.
ATmega48P/88P/168P 10.2 BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 28-6 on page 293, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 10-1 on page 40. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.
10.5 Power-down Mode When the SM[2:0] bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2wire Serial Interface address watch, and the Watchdog continue operating (if enabled).
ATmega48P/88P/168P 10.9 Power Reduction Register The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 46, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
10.10.5 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to ”Watchdog Timer” on page 51 for details on how to configure the Watchdog Timer. 10.10.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power.
ATmega48P/88P/168P 10.11 Register Description 10.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 7:4 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero.
be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to zero within four clock cycles. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. • Bit 5 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description.
ATmega48P/88P/168P 11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For the ATmega168P, the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the ATmega48P and ATmega88P, the instruction placed at the Reset Vector must be an RJMP – Relative Jump – instruction to the reset handling routine.
Figure 11-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER RSTDISBL Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characteristics” on page 314.
ATmega48P/88P/168P Figure 11-3. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 11.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”System and Reset Characteristics” on page 314) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Figure 11-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 11.6 Watchdog System Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 51 for details on operation of the Watchdog Timer. Figure 11-6. Watchdog System Reset During Operation CC CK 11.
ATmega48P/88P/168P ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 11.8 11.8.1 Watchdog Timer Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 11.8.
mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2.
ATmega48P/88P/168P Assembly Code Example(1) WDT_off: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<
The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer. Assembly Code Example(1) WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR r16, (1<
ATmega48P/88P/168P 11.9 11.9.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – – – – WDRF BORF EXTRF PORF Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 MCUSR See Bit Description • Bit 7:4 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero.
WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied. Table 11-1.
ATmega48P/88P/168P Table 11-2. Watchdog Timer Prescale Select (Continued) WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.0V 1 0 0 0 512K (524288) cycles 4.0 s 1 0 0 1 1024K (1048576) cycles 8.
12. Interrupts This section describes the specifics of the interrupt handling as performed in ATmega48P/88P/168P. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 15. The interrupt vectors in ATmega48P, ATmega88P and ATmega168P are generally the same, with the following differences: • Each Interrupt Vector occupies two instruction words in ATmega168P, and one instruction word in ATmega48P and ATmega88P.
ATmega48P/88P/168P Table 12-1. Reset and Interrupt Vectors in ATmega48P (Continued) Vector No.
12.2 Interrupt Vectors in ATmega88P Table 12-2. Reset and Interrupt Vectors in ATmega88P Vector No.
ATmega48P/88P/168P Table 12-3. Reset and Interrupt Vectors Placement in ATmega88P(1) BOOTRST IVSEL 1 Note: Reset Address Interrupt Vectors Start Address 0 0x000 0x001 1 1 0x000 Boot Reset Address + 0x001 0 0 Boot Reset Address 0x001 0 1 Boot Reset Address Boot Reset Address + 0x001 1. The Boot Reset Address is shown in Table 27-7 on page 287. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega88P is: Address Labels Code Comments 0x000 RESET: ldi 0x001 out SPH,r16 r16,high(RAMEND); Main program start 0x002 ldi r16,low(RAMEND) 0x003 0x004 out sei SPL,r16 0x005 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx ; .
ATmega48P/88P/168P 12.3 0xC1B out SPH,r16 0xC1C ldi r16,low(RAMEND) 0xC1D 0xC1E out sei SPL,r16 0xC1F ; Set Stack Pointer to top of RAM ; Enable interrupts xxx Interrupt Vectors in ATmega168P Table 12-4. VectorNo.
Table 12-5 on page 64 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 12-5.
ATmega48P/88P/168P 0x0034 out SPH,r16 0x0035 ldi r16, low(RAMEND) 0x0036 out SPL,r16 0x0037 sei 0x0038 ... ; Enable interrupts ... ... ; Set Stack Pointer to top of RAM xxx ...
Address Labels Code Comments ; .org 0x1C00 0x1C00 jmp RESET ; Reset handler 0x1C02 jmp EXT_INT0 ; IRQ0 Handler 0x1C04 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x1C32 jmp SPM_RDY ; Store Program Memory Ready Handler ; 12.4 0x1C33 RESET: ldi 0x1C34 out SPH,r16 r16,high(RAMEND); Main program start 0x1C35 ldi r16,low(RAMEND) 0x1C36 0x1C37 out sei SPL,r16 0x1C38 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx Register Description 12.4.
ATmega48P/88P/168P • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
13. External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT[23:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT[23:0] pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT[23:16] pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT[14:8] pin toggles.
ATmega48P/88P/168P 13.2 13.2.1 Register Description EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit 7 6 5 4 3 2 1 0 (0x69) – – – – ISC11 ISC10 ISC01 ISC00 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EICRA • Bit 7:4 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero.
13.2.2 EIMSK – External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 0x1D (0x3D) – – – – – – INT1 INT0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 EIMSK • Bit 7:2 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
ATmega48P/88P/168P 13.2.4 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 (0x68) – – – – – PCIE2 PCIE1 PCIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCICR • Bit 7:3 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 2 – PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 13.2.
ATmega48P/88P/168P 14. I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 14-2.
ATmega48P/88P/168P If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 14.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 14.2.
Figure 14-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega48P/88P/168P Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down.
ATmega48P/88P/168P Table 14-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 14-5 on page 78 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 14-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
14.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-3. Table 14-3.
ATmega48P/88P/168P AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PB6 is disconnected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt source. If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.
(one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source. • ICP1/CLKO/PCINT0 – Port B, Bit 0 ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1. CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin.
ATmega48P/88P/168P Table 14-5. 14.3.2 Overriding Signals for Alternate Functions in PB3..
The alternate pin configuration is as follows: • RESET/PCINT14 – Port C, Bit 6 RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an I/O pin. If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0. PCINT14: Pin Change Interrupt source 14.
ATmega48P/88P/168P • ADC1/PCINT9 – Port C, Bit 1 PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog power. PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source. • ADC0/PCINT8 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source.
Table 14-8. 14.3.
ATmega48P/88P/168P The alternate pin configuration is as follows: • AIN1/OC2B/PCINT23 – Port D, Bit 7 AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT23: Pin Change Interrupt source 23. The PD7 pin can serve as an external interrupt source. • AIN0/OC0A/PCINT22 – Port D, Bit 6 AIN0, Analog Comparator Positive Input.
• INT0/PCINT18 – Port D, Bit 2 INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source. PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt source. • TXD/PCINT17 – Port D, Bit 1 TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1. PCINT17: Pin Change Interrupt source 17. The PD1 pin can serve as an external interrupt source.
ATmega48P/88P/168P Table 14-11. Overriding Signals for Alternate Functions in PD3..
14.4 14.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – BODS BODSE PUD – – IVSEL IVCE Read/Write R R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATmega48P/88P/168P 14.4.8 PORTD – The Port D Data Register Bit 14.4.9 7 6 5 4 3 2 1 0 0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRD – The Port D Data Direction Register Bit 14.4.
15. 8-bit Timer/Counter0 with PWM 15.1 Features • • • • • • • 15.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
ATmega48P/88P/168P Figure 15-1. 8-bit Timer/Counter Block Diagram Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA Fixed TOP Value Waveform Generation = OCnB OCRnB TCCRnA 15.2.1 OCnB (Int.Req.) TCCRnB Definitions Many register and bit references in this section are written in general form.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times.
ATmega48P/88P/168P The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B. For more details about advanced counting sequences and waveform generation, see ”Modes of Operation” on page 97.
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly. 15.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit.
ATmega48P/88P/168P Figure 15-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
15.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero.
ATmega48P/88P/168P the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------2 ⋅ N ⋅ ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 15.7.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (see Table 15-6 on page 105).
ATmega48P/88P/168P Figure 15-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
symmetry around BOTTOM the OCnx value at MAX must correspond to the result of an upcounting Compare Match. • The timer starts counting from a value higher than the one in OCRnx, and for that reason misses the Compare Match and hence the OCnx change that would have happened on the way up. 15.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures.
ATmega48P/88P/168P Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 15-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where OCR0A is TOP. Figure 15-11.
15.9 15.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to.
ATmega48P/88P/168P Table 15-4 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 15-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting.
Table 15-7 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Table 15-7. Compare Output Mode, Phase Correct PWM Mode(1) COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
ATmega48P/88P/168P 15.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
Table 15-9. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
ATmega48P/88P/168P 15.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6E) – – – – – OCIE0B OCIE0A TOIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bits 7:3 – Reserved These bits are reserved bits in the ATmega48P/88P/168P and will always read as zero.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting.
ATmega48P/88P/168P 16. 16-bit Timer/Counter1 with PWM 16.1 Features • • • • • • • • • • • 16.2 True 16-bit Design (i.e.
Figure 16-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 16.2.1 TCCRnB 1.
ATmega48P/88P/168P put Compare Units” on page 120. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ... Note: 1. See ”About Code Examples” on page 8. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O.
ATmega48P/88P/168P Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1.
Assembly Code Example(1) TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1.
ATmega48P/88P/168P 16.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surroundings. Figure 16-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit.
ATmega48P/88P/168P tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers” on page 113. 16.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 16.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle.
ATmega48P/88P/168P prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
16.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 16-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega48P/88P/168P non-PWM modes refer to Table 16-1 on page 132. For fast PWM mode refer to Table 16-2 on page 133, and for phase correct and phase and frequency correct PWM refer to Table 16-3 on page 133. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 16.9 Modes of Operation The mode of operation, i.e.
Figure 16-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega48P/88P/168P The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values.
ATmega48P/88P/168P 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running.
ATmega48P/88P/168P the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
ATmega48P/88P/168P Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
Figure 16-13 shows the same timing data, but with the prescaler enabled. Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 16.11 Register Description 16.11.
ATmega48P/88P/168P Table 16-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 16-2. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
Waveform Generation Mode Bit Description(1) Table 16-4.
ATmega48P/88P/168P When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description.
16.11.4 TCNT1H and TCNT1L – Timer/Counter1 Bit 7 6 5 4 3 (0x85) TCNT1[15:8] (0x84) TCNT1[7:0] 2 1 0 TCNT1H TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter.
ATmega48P/88P/168P 16.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 7, 6 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin.
ATmega48P/88P/168P 17. Timer/Counter0 and Timer/Counter1 Prescalers ”8-bit Timer/Counter0 with PWM” on page 92 and ”16-bit Timer/Counter1 with PWM” on page 111 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle.
ATmega48P/88P/168P 17.4 17.4.1 Register Description GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSRASY PSRSYNC Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode.
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features • • • • • • • 18.2 Single Channel Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B) Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock Overview Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
ATmega48P/88P/168P 18.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
Figure 18-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT2 in the following. top Signalizes that TCNT2 has reached maximum value.
ATmega48P/88P/168P Figure 18-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
The setup of the OC2x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2x1:0 bits are not double buffered together with the compare value. Changing the COM2x1:0 bits will take effect immediately. 18.
ATmega48P/88P/168P 18.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 18-5 on page 157. For fast PWM mode, refer to Table 18-6 on page 157, and for phase correct PWM refer to Table 18-7 on page 158.
Figure 18-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega48P/88P/168P In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 18-6. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2.
generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 18.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation.
ATmega48P/88P/168P output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (See Table 18-4 on page 157). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output.
Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 18-10 shows the setting of OCF2A in all modes except CTC mode. Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 18-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 18-11.
ATmega48P/88P/168P 18.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. b. Select clock source by setting AS2 as appropriate. c.
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.
ATmega48P/88P/168P (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. For Timer/Counter2, the possible prescaled selections are: clk T2S /8, clk T2S /32, clk T2S /64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
18.11 Register Description 18.11.1 TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to.
ATmega48P/88P/168P Table 18-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 18-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting. 1 1 Set OC2A on Compare Match when up-counting.
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See ”Phase Correct PWM Mode” on page 150 for more details. Table 18-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 18-7. COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected.
ATmega48P/88P/168P 18.11.2 TCCR2B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 FOC2A FOC2B – – WGM22 CS22 CS21 CS20 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB1) TCCR2B • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
Table 18-9. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped).
ATmega48P/88P/168P 18.11.6 TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x70) – – – – – OCIE2B OCIE2A TOIE2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK2 • Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match B interrupt is enabled.
18.11.8 ASSR – Asynchronous Status Register Bit 7 6 5 4 3 2 1 0 (0xB6) – EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB Read/Write R R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 7 – RES: Reserved bit This bit is reserved and will always read as zero.
ATmega48P/88P/168P The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 18.11.
19. SPI – Serial Peripheral Interface 19.1 Features • • • • • • • • 19.
ATmega48P/88P/168P The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2 on page 165. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 19-1 on page 166. For more details on automatic port overrides, refer to ”Alternate Port Functions” on page 78. Table 19-1.
ATmega48P/88P/168P Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega48P/88P/168P 19.3 19.3.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
Figure 19-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 19-4.
ATmega48P/88P/168P 19.5 19.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 19-5. 19.5.
ATmega48P/88P/168P 19.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
20. USART0 20.1 Features • • • • • • • • • • • • 20.
ATmega48P/88P/168P Figure 20-1. USART Block Diagram(1) Clock Generator UBRRn [H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCKn Transmitter TX CONTROL DATA BUS UDRn(Transmit) PARITY GENERATOR 20.3 TxDn Receiver UCSRnA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDRn (Receive) PARITY CHECKER UCSRnB RxDn UCSRnC 1. Refer to Figure 1-1 on page 2 and Table 14-9 on page 86 for USART0 pin placement.
Figure 20-2 shows a block diagram of the clock generation logic. Figure 20-2. Clock Generation Logic, Block Diagram UBRRn U2Xn foscn Prescaling Down-Counter UBRRn+1 /2 /4 /2 0 1 0 OSC DDR_XCKn xcki XCKn Pin Sync Register Edge Detector 1 0 UMSELn 1 xcko UCPOLn DDR_XCKn txclk 1 0 rxclk Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki operation. 20.3.1 Input from XCK pin (internal Signal).
ATmega48P/88P/168P Table 20-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Table 20-1.
20.3.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 20-2 for details. External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver.
ATmega48P/88P/168P A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 20-4 illustrates the possible combinations of the frame formats.
20.5 USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization.
ATmega48P/88P/168P For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRnH, r17 out UBRRnL, r16 ; Enable receiver and transmitter ldi r16, (1<
chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 20.6.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame.
ATmega48P/88P/168P show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
ATmega48P/88P/168P bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
ATmega48P/88P/168P 20.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 20.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e.
ATmega48P/88P/168P Figure 20-5. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
ATmega48P/88P/168P Table 20-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 20-3.
nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
ATmega48P/88P/168P 20.10 Register Description 20.10.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.
ATmega48P/88P/168P • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn pin when enabled.
• Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 20-5.
ATmega48P/88P/168P Table 20-8. Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin) 0 Rising XCKn Edge Falling XCKn Edge 1 Falling XCKn Edge Rising XCKn Edge UCPOLn 20.10.
Table 20-9. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 1.0000 MHz fosc = 1.8432 MHz Baud Rate (bps) UBRRn 2400 25 0.2% 51 0.2% 47 4800 12 0.2% 25 0.2% 9600 6 -7.0% 12 14.4k 3 8.5% 19.2k 2 28.8k U2Xn = 0 U2Xn = 1 UBRRn Error 0.0% 95 0.0% 51 0.2% 103 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.
ATmega48P/88P/168P Table 20-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz Baud Rate (bps) U2Xn = 0 fosc = 4.0000 MHz U2Xn = 1 U2Xn = 0 fosc = 7.3728 MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.
Table 20-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.
ATmega48P/88P/168P Table 20-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.
21. USART in SPI Mode 21.1 Features • • • • • • • • 21.
ATmega48P/88P/168P Table 21-1. Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate(1) Equation for Calculating UBRRn Value f OSC BAUD = -------------------------------------2 ( UBRRn + 1 ) f OSC UBRRn = -------------------–1 2BAUD Synchronous Master mode Note: 21.4 1.
Figure 21-1. UCPHAn and UCPOLn data transfer timing diagrams. UCPHA=0 UCPHA=1 UCPOL=0 21.5 UCPOL=1 XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) XCK XCK Data setup (TXD) Data setup (TXD) Data sample (RXD) Data sample (RXD) Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits.
ATmega48P/88P/168P be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume polling (no interrupts enabled). The baud rate is given as a function parameter.
21.6 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
ATmega48P/88P/168P Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDRn,r16 ; Wait for data to be received USART_MSPIM_Wait_RXCn: sbis UCSRnA, RXCn rjmp USART_MSPIM_Wait_RXCn ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
21.7 AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: • Master mode timing diagram. • The UCPOLn bit functionality is identical to the SPI CPOL bit. • The UCPHAn bit functionality is identical to the SPI CPHA bit. • The UDORDn bit functionality is identical to the SPI DORD bit. However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI.
ATmega48P/88P/168P 21.8 Register Description The following section describes the registers used for SPI operation using the USART. 21.8.1 UDRn – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation. See “UDRn – USART I/O Data Register n” on page 193. 21.8.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag.
ATmega48P/88P/168P • Bit 5:3 – Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnC is written. • Bit 2 – UDORDn: Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to the Frame Formats section page 4 for details.
22. 2-wire Serial Interface 22.1 Features • • • • • • • • • • • 22.
ATmega48P/88P/168P 22.2.1 TWI Terminology The following definitions are frequently encountered in this section. Table 22-1. TWI Terminology Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus.
22.3 22.3.1 Data Transfer and Frame Format Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. Figure 22-2. Data Validity SDA SCL Data Stable Data Stable Data Change 22.3.2 START and STOP Conditions The Master initiates and terminates a data transmission.
ATmega48P/88P/168P 22.3.3 Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a Slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle.
Figure 22-5. Data Packet Format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 7 SLA+R/W 22.3.5 STOP, REPEATED START or Next Data Byte Data Byte Combining Address and Data Packets into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal.
ATmega48P/88P/168P masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. • Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process. The wired-ANDing of the bus lines is used to solve both these problems.
Figure 22-8. Arbitration Between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition. It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
ATmega48P/88P/168P 22.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 22-9. All registers drawn in a thick line are accessible through the AVR data bus. Figure 22-9.
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation: CPU Clock frequency SCL frequency = ----------------------------------------------------------------------------------------16 + 2(TWBR) ⋅ ( PrescalerValue ) • TWBR = Value of the TWI Bit Rate Register. • PrescalerValue = Value of the prescaler, see Table 22-7 on page 241. Note: 22.5.
ATmega48P/88P/168P able. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The TWINT Flag is set in the following situations: • After the TWI has transmitted a START/REPEATED START condition. • After the TWI has transmitted SLA+R/W. • After the TWI has transmitted an address byte. • After the TWI has lost arbitration. • After the TWI has been addressed by own slave address or general call.
Application Action Figure 22-10. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCR to initiate transmission of START TWI Hardware Action TWI bus 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, makin sure that TWINT is written to one, and TWSTA is written to zero. START SLA+W 2. TWINT set. Status code indicates START condition sent 5.
ATmega48P/88P/168P not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a Slave acknowledged the packet or not. 7.
Assembly Code Example C Example ldi r16, (1<
ATmega48P/88P/168P 22.7 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
Figure 22-11. Data Transfer in Master Transmitter Mode VCC Device 1 Device 2 MASTER TRANSMITTER SLAVE RECEIVER Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag.
ATmega48P/88P/168P After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 22-2.
Figure 22-12.
ATmega48P/88P/168P Figure 22-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 22-3.
ATmega48P/88P/168P Figure 22-14. Formats and States in the Master Receiver Mode MR Successfull reception from a slave receiver S SLA $08 R A DATA A $40 DATA $50 A P $58 Next transfer started with a repeated start condition RS SLA R $10 Not acknowledge received after the slave address A W P $48 MT Arbitration lost in slave address or data byte A or A Other master continues A $38 Arbitration lost and addressed as slave A $68 From master to slave 22.7.
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
ATmega48P/88P/168P Table 22-4.
Figure 22-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
ATmega48P/88P/168P To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
Table 22-5.
ATmega48P/88P/168P Figure 22-18. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to slave From slave to master 22.7.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation.
ATmega48P/88P/168P • Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit.
• Bit 7 – TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine.
ATmega48P/88P/168P • Bit 0 – TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high. 22.9.3 TWSR – TWI Status Register Bit 7 6 5 4 3 2 1 0 TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 Read/Write R R R R R R R/W R/W Initial Value 1 1 1 1 1 0 0 0 (0xB9) TWSR • Bits 7:3 – TWS: TWI Status These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus.
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly. • Bits 7:0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire Serial Bus. 22.9.
ATmega48P/88P/168P Figure 22-22. TWI Address Match Logic, Block Diagram TWAR0 Address Match Address Bit 0 TWAMR0 Address Bit Comparator 0 Address Bit Comparator 6..1 • Bit 0 – Res: Reserved Bit This bit is an unused bit in the ATmega48P/88P/168P, and will always read as zero.
23. Analog Comparator 23.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega48P/88P/168P . Table 23-1. 23.3 23.3.1 Analog Comparator Multiplexed Input ACME ADEN MUX2..
certain time for the voltage to stabilize. If not stabilized, the first conversion may give a wrong value. See ”Internal Voltage Reference” on page 50 • Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0.
ATmega48P/88P/168P 23.3.3 DIDR1 – Digital Input Disable Register 1 Bit 7 6 5 4 3 2 1 0 (0x7F) – – – – – – AIN1D AIN0D Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 DIDR1 • Bit 7:2 – Reserved These bits are unused bits in the ATmega48P/88P/168P, and will always read as zero. • Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled.
24. Analog-to-Digital Converter 24.1 Features • • • • • • • • • • • • • • 24.2 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 - 260 µs Conversion Time Up to 76.9 kSPS (Up to 15 kSPS at Maximum Resolution) 6 Multiplexed Single Ended Input Channels 2 Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF Package only) Temperature Sensor Input Channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.
ATmega48P/88P/168P Figure 24-1. Analog to Digital Converter Block Schematic Operation, ADC CONVERSION COMPLETE IRQ ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADFR ADEN ADSC MUX1 15 ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX3 MUX2 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS MUX DECODER CHANNEL SELECTION PRESCALER AVCC CONVERSION LOGIC INTERNAL 1.
read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. 24.
ATmega48P/88P/168P If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 24.4 Prescaling and Conversion Timing Figure 24-3.
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 24-1 on page 253. Figure 24-4.
ATmega48P/88P/168P Figure 24-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 24-1. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 Condition Auto Triggered conversions 24.
24.5.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
ATmega48P/88P/168P 24.6.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 24-8. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
and ADC5) will only affect the conversion on ADC4 and ADC5 and not the other ADC channels. Analog Ground Plane PC2 (ADC2) PC3 (ADC3) PC4 (ADC4/SDA) PC5 (ADC5/SCL) VCC GND Figure 24-9. ADC Power Connections PC1 (ADC1) PC0 (ADC0) ADC7 ADC6 AVCC 100nF AREF 10µH GND PB5 24.6.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
ATmega48P/88P/168P Figure 24-10. Offset Error Output Code Ideal ADC Actual ADC Offset Error VREF Input Voltage • Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 24-11.
Figure 24-12. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 24-13.
ATmega48P/88P/168P 24.7 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN ⋅ 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 24-3 on page 260 and Table 24-4 on page 261). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
24.9 24.9.1 Register Description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 24-3.
ATmega48P/88P/168P Table 24-4. Input Channel Selections MUX[3:0] Note: 24.9.2 Single Ended Input 0000 ADC0 0001 ADC1 0010 ADC2 0011 ADC3 0100 ADC4 0101 ADC5 0110 ADC6 0111 ADC7 1000 ADC8(1) 1001 (reserved) 1010 (reserved) 1011 (reserved) 1100 (reserved) 1101 (reserved) 1110 1.1V (VBG) 1111 0V (GND) 1. For Temperature Sensor.
• Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ATmega48P/88P/168P 24.9.3 ADCL and ADCH – The ADC Data Register 24.9.3.1 ADLAR = 0 Bit 15 14 13 12 11 10 9 8 (0x79) – – – – – – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 24.9.3.
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 24-6. 24.9.
ATmega48P/88P/168P 25. debugWIRE On-chip Debug System 25.1 Features • • • • • • • • • • 25.
When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for debugWIRE functionality. • Connecting the RESET pin directly to VCC will not work. • Capacitors connected to the RESET pin must be disconnected when using debugWire. • All external reset sources must be disconnected. 25.
ATmega48P/88P/168P 26. Self-Programming the Flash, ATmega48P 26.1 Overview In ATmega48P, there is no Read-While-Write support, and no separate Boot Loader Section. The SPM instruction can be executed from the entire Flash. The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 26.1.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • The CPU is halted during the Page Write operation. 26.
ATmega48P/88P/168P 26.2.1 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 26.2.
26.2.3 Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly.
ATmega48P/88P/168P 26.2.5 Simple Assembly Code Example for a Boot Loader Note that the RWWSB bit will always be read as zero in ATmega48P. Nevertheless, it is recommended to check this bit as shown in the code example, to ensure compatibility with devices supporting Read-While-Write.
sbci YH, high(PAGESIZEB) Rdloop: lpm r0, Z+ ld r1, Y+ cpse r0, r1 rjmp Error sbiw loophi:looplo, 1 brne Rdloop ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega48P/88P/168P 26.3 26.3.1 Register Description’ SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations.
• Bit 0 – SELFPRGEN: Self Programming Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SELFPRGEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored.
ATmega48P/88P/168P 27. Boot Loader Support – Read-While-Write Self-Programming, ATmega88P and ATmega168P 27.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 27.2 1.
27.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
ATmega48P/88P/168P Figure 27-1. Read-While-Write vs.
Figure 27-2.
ATmega48P/88P/168P Table 27-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
27.7 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 28-9 on page 295), the Program Counter can be treated as having two different sections.
ATmega48P/88P/168P Alternative 1, fill the buffer before a Page Erase • Fill temporary page buffer • Perform a Page Erase • Perform a Page Write Alternative 2, fill the buffer after Page Erase • Perform a Page Erase • Fill temporary page buffer • Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten.
27.8.4 Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SELFPRGEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in ”Interrupts” on page 58. 27.8.
ATmega48P/88P/168P instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in the Instruction set Manual.
Table 27-5. Signature Byte Z-Pointer Address Device Signature Byte 1 0x0000 Device Signature Byte 2 0x0002 Device Signature Byte 3 0x0004 RC Oscillator Calibration Byte 0x0001 Note: 27.8.11 Signature Row Addressing All other addresses are reserved for future use. Preventing Flash Corruption During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly.
ATmega48P/88P/168P ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega48P/88P/168P 27.8.14 ATmega88P Boot Loader Parameters In Table 27-7 through Table 27-9, the parameters used in the description of the self programming are given. Table 27-7.
27.8.15 ATmega168P Boot Loader Parameters In Table 27-10 through Table 27-12, the parameters used in the description of the self programming are given. Table 27-10.
ATmega48P/88P/168P 27.9 27.9.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Zpointer. The data in R1 and R0 are ignored.
ATmega48P/88P/168P 28. Memory Programming 28.1 Program And Data Memory Lock Bits The ATmega88P/168P/328P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 28-2. The Lock bits can only be erased to “1” with the Chip Erase command. The ATmega48P has no separate Boot Loader section. The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed (“0”), otherwise it is disabled. Table 28-1.
Table 28-3. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
ATmega48P/88P/168P Table 28-5. Extended Fuse Byte for ATmega88P/168P Extended Fuse Byte Bit No Description Default Value – 7 – 1 – 6 – 1 – 5 – 1 – 4 – 1 – 3 – 1 2 Select Boot Size (see Table 27-7 on page 287 and Table 27-10 on page 288 for details) 0 (programmed)(1) BOOTSZ0 1 Select Boot Size (see Table 27-7 on page 287 and Table 27-10 on page 288 for details) 0 (programmed)(1) BOOTRST 0 Select Reset Vector 1 (unprogrammed) BOOTSZ1 Note: 1.
Table 28-7. Fuse Low Byte Low Fuse Byte Bit No Description Default Value CKDIV8(4) 7 Divide clock by 8 0 (programmed) (3) 6 Clock output 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(1) SUT0 4 Select start-up time 0 (programmed)(1) CKSEL3 3 Select Clock source 0 (programmed)(2) CKSEL2 2 Select Clock source 0 (programmed)(2) CKSEL1 1 Select Clock source 1 (unprogrammed)(2) CKSEL0 0 Select Clock source 0 (programmed)(2) CKOUT Note: 1.
ATmega48P/88P/168P 28.5 Page Size Table 28-9. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB ATmega48P 2K words (4K bytes) 32 words PC[4:0] 64 PC[10:5] 10 ATmega88P 4K words (8K bytes) 32 words PC[4:0] 128 PC[11:5] 11 64 words PC[5:0] 128 PC[12:6] 12 ATmega168P 8K words (16K bytes) Table 28-10. No. of Words in a Page and No. of Pages in the EEPROM 28.6 Device EEPROM Size Page Size PCWORD No.
Figure 28-1. Parallel Programming +4.5 - 5.5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12 V VCC +4.5 - 5.5V AVCC PC[1:0]:PB[5:0] DATA RESET BS2 PC2 XTAL1 GND Note: VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 4.5 - 5.5V Table 28-11.
ATmega48P/88P/168P Table 28-13. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 28-14. Command Byte Bit Coding Command Byte 28.7 28.7.
4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 5. Wait until VCC actually reaches 4.5 -5.5V before giving any parallel programming commands. 6. Exit Programming mode by power the device down or by bringing RESET pin to 0V. 28.7.2 Considerations for Efficient Programming The loaded command and address are retained in the device during programming.
ATmega48P/88P/168P 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. E. Latch Data 1.
Figure 28-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 28-9 on page 295. Figure 28-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR.
ATmega48P/88P/168P 5. E: Latch data (give PAGEL a positive pulse). K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 28-4 for signal waveforms). Figure 28-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR.
28.7.8 Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to ”Programming the Flash” on page 298 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. 28.7.
ATmega48P/88P/168P 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase. 28.7.
28.7.14 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to ”Programming the Flash” on page 298 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. 28.7.15 28.8 Parallel Programming Characteristics For chracteristics of the Parallel Programming, see ”Parallel Programming Characteristics” on page 320.
ATmega48P/88P/168P 28.8.1 Serial Programming Pin Mapping Table 28-15. Pin Mapping Serial Programming 28.8.2 Symbol Pins I/O Description MOSI PB3 I Serial Data in MISO PB4 O Serial Data out SCK PB5 I Serial Clock Serial Programming Algorithm When writing serial data to the ATmega48P/88P/168P, data is clocked on the rising edge of SCK. When reading data from the ATmega48P/88P/168P, data is clocked on the falling edge of SCK. See Figure 28-9 for timing details.
not used, the used must wait at least tWD_EEPROM before issuing the next byte (See Table 28-16). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 28-16.
ATmega48P/88P/168P Table 28-17.
Figure 28-8. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Adr MSB A Bit 15 B Byte 3 Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Adr MSB Bit 15 B 0 Byte 3 Byte 4 Adrr LSB B 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 28.8.4 SPI Serial Programming Characteristics Figure 28-9.
ATmega48P/88P/168P 29. Electrical Characteristics 29.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter RRST Reset Pull-up Resistor RPU I/O Pin Pull-up Resistor VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Condition Min. Typ. Max. Units 30 60 kΩ 20 50 kΩ 40 mV 50 nA <10 -50 750 500 ns 1.
ATmega48P/88P/168P 4. Maximum values are characterized values and not test limits in production. 29.2.2 ATmega88P DC Characteristics TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Power Supply Current(1) ICC (3)(4) Power-save mode Power-down mode(3) Notes: 1. 2. 3. 4. 29.2.3 Typ.(2) Max. Units Active 1 MHz, VCC = 2V 0.3 0.5 mA Active 4 MHz, VCC = 3V 1.7 2.5 mA Active 8 MHz, VCC = 5V 6.3 9 mA Idle 1 MHz, VCC = 2V 0.05 0.
3. The current consumption values include input leakage current. 4. Maximum values are characterized values and not test limits in production. 29.3 Speed Grades Maximum frequency is dependent on VCC. As shown in Figure 29-1 and Figure 29-2, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 29-1. Maximum Frequency vs. VCC, ATmega48P/88P/168PV 20 MHz 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 4.5V 5.5V Figure 29-2. Maximum Frequency vs.
ATmega48P/88P/168P 29.4 Clock Characteristics 29.4.1 Calibrated Internal RC Oscillator Accuracy Table 29-1. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0 MHz 3V 25°C ±10% User Calibration 7.3 - 8.1 MHz 1.8V - 5.5V(1) 2.7V - 5.5V(2) -40°C - 85°C ±1% Notes: 1. Voltage range for ATmega48PV/88PV/168PV. 2. Voltage range for ATmega48P/88P/168P. 29.4.2 External Clock Drive Waveforms Figure 29-3.
29.5 System and Reset Characteristics Table 29-3. Symbol Reset, Brown-out and Internal Voltage Characteristics(1) Parameter Min Typ Max Units Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.6 V Power-on Reset Threshold Voltage (falling)(2) 0.6 1.3 1.6 V SRON Power-on Slope Rate 0.01 10 V/ms VRST RESET Pin Threshold Voltage 0.2 VCC 0.9 VCC V tRST Minimum pulse width on RESET Pin 2.
ATmega48P/88P/168P 29.6 SPI Timing Characteristics See Figure 29-4 and Figure 29-5 for details. Table 29-5. SPI Timing Parameters Description Mode 1 SCK period Master See Table 19-5 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 29-4. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 8 7 MOSI (Data Output) MSB ... LSB Figure 29-5. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 316 MSB 17 ...
ATmega48P/88P/168P 29.7 2-wire Serial Interface Characteristics Table 29-6 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega48P/88P/168P 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 29-6. Table 29-6. 2-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) VOL(1) tr(1) tof(1) Min Max Units Input Low-voltage -0.5 0.3 VCC V Input High-voltage 0.7 VCC VCC + 0.
3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency 5. This requirement applies to all ATmega48P/88P/168P 2-wire Serial Interface operation. Other devices connected to the 2wire Serial Bus need only obey the general fSCL requirement. Figure 29-6.
ATmega48P/88P/168P 29.8 ADC Characteristics – Preliminary Data Table 29-7. Symbol ADC Characteristics Parameter Condition Min Resolution VIN Units Bits VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz 4.5 LSB VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 2 LSB VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 4.5 LSB Integral Non-Linearity (INL) VREF = 4V, VCC = 4V, ADC clock = 200 kHz 0.
29.9 Parallel Programming Characteristics Table 29-8. Symbol Parameter Min VPP Programming Enable Voltage 11.
ATmega48P/88P/168P Figure 29-7. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 29-8.
30. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
ATmega48P/88P/168P Figure 30-2. Active Supply Current vs. Frequency (1 - 20 MHz). 20 5.5 V 16 ICC (mA) 5.0 V 4.5 V 12 4.0 V 8 3.3 V 4 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-3. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.18 25 °C 0.16 85 °C -40 °C 0.14 ICC (mA) 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 2 1.8 85 °C 25 °C -40 °C 1.6 1.4 ICC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-5. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 10 9 85 °C 25 °C -40 °C 8 7 ICC (mA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P 30.1.2 Idle Supply Current Figure 30-6. Idle Supply Current vs. Low Frequency (0.1-1.0 MHz). 0.4 0.35 0.3 5.5 V ICC (mA) 0.25 5.0 V 0.2 4.5 V 4.0 V 0.15 3.3 V 0.1 2.7 V 0.05 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-7. Idle Supply Current vs. Frequency (1-20 MHz). 6 5 5.5 V ICC (mA) 4 5.0 V 4.5 V 3 4.0V 2 3.3V 1 2.7V 1.
Figure 30-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.06 85 °C 0.05 25 °C 0.04 ICC (mA) -40 °C 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 0.9 0.8 0.7 ICC (mA) 0.6 85 °C 25 °C -40 °C 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-10. Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz). 3 2.5 85 °C 25 °C -40 °C ICC (mA) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.1.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
Table 30-2. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 30-1 on page 322 and Figure 30-2 on page 323) Additional Current consumption compared to Idle with external clock (see Figure 30-6 on page 325 and Figure 30-7 on page 325) PRUSART0 1.9% 9.1% PRTWI 3.1% 14.8% PRTIM2 3.5% 16.6% PRTIM1 3.4% 16.1% PRTIM0 0.8% 3.9% PRSPI 2.8% 13.4% PRADC 3.3% 15.
ATmega48P/88P/168P Figure 30-12. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled). 18 16 14 ICC (uA) 12 10 -40 °C 85 °C 25 °C 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.1.5 Power-save Supply Current Figure 30-13. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running). 1.6 25 °C 1.4 1.2 ICC (uA) 1 0.8 0.6 0.4 0.2 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.
30.1.6 Standby Supply Current Figure 30-14. Standby Supply Current vs. Vcc (Watchdog Timer Disabled). 0.2 6MHz_xtal 0.18 6MHz_res 0.16 ICC (mA) 0.14 4MHz_xtal 0.12 4MHz_res 0.1 2MHz_res 0.08 2MHz_xtal 450kHz_res 0.06 0.04 0.02 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 5.8 VCC (V) 30.1.7 Pin Pull-Up Figure 30-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V). 90 80 70 IOP (uA) 60 50 40 30 20 85 °C 25 °C -40 °C 10 0 0 0.5 1 1.5 2 2.
ATmega48P/88P/168P Figure 30-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V). 90 80 70 IOP (uA) 60 50 40 30 20 85 °C 25 °C -40 °C 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 30-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V).
Figure 30-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V). 45 40 35 IRESET (uA) 30 25 20 15 10 5 85 °C 25 °C -40 °C 0 -5 0 0.2 0.4 0.6 0.8 1 VRESET (V) 1.2 1.4 1.6 1.8 2 Figure 30-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V). 70 60 IRESET (uA) 50 40 30 20 10 25 °C -40 °C 85 °C 0 -10 332 0 0.5 1 1.5 VRESET (V) 2 2.
ATmega48P/88P/168P Figure 30-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V). 140 120 IRESET (uA) 100 80 60 40 20 25 °C -40 °C 85 °C 0 -20 30.1.8 0 1 2 3 VRESET (V) 4 5 6 Pin Driver Strength Figure 30-21. I/O Pin Output Voltage vs. Sink Current (VCC = 3 V). 1 85 °C 0.9 0.8 25 °C 0.7 -40 °C VOL (V) 0.6 0.5 0.4 0.3 0.2 0.
Figure 30-22. I/O Pin Output Voltage vs. Sink Current (VCC = 5 V). 0.7 85 °C 0.6 25 °C 0.5 VOL (V) -40 °C 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (mA) Figure 30-23. I/O Pin Output Voltage vs. Source Current (Vcc = 3 V). 3.5 3 2.5 VOH (V) -40 °C 25 °C 2 85 °C 1.5 1 0.
ATmega48P/88P/168P Figure 30-24. I/O Pin Output Voltage vs. Source Current(VCC = 5 V). 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -40 °C 4.5 25 °C 4.4 85 °C 4.3 0 5 10 15 20 25 IOH (mA) 30.1.9 Pin Threshold and Hysteresis Figure 30-25. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’). 3 85 °C 25 °C -40 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-26. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-27. I/O Pin Input Hysteresis vs. VCC. 0.6 Input Hysteresis (mV) 0.5 85 °C -40 °C 25 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-28. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-29. Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-30. Reset Pin Input Hysteresis vs. VCC. 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 85 °C 25 °C -40 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.1.10 BOD Threshold Figure 30-31. BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V). 1.9 1.88 1.86 Threshold (V) 1.84 Rising Vcc 1.82 1.8 Falling Vcc 1.78 1.76 1.74 1.72 1.
ATmega48P/88P/168P Figure 30-32. BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V). 2.9 2.85 Threshold (V) 2.8 Rising Vcc 2.75 2.7 Falling Vcc 2.65 2.6 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 90 100 Temperature (°C) Figure 30-33. BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V). 4.5 4.45 Threshold (V) 4.4 4.35 Rising Vcc 4.3 4.25 Falling Vcc 4.
30.1.11 Internal Oscilllator Speed Figure 30-34. Watchdog Oscillator Frequency vs. Temperature. 113 112 111 FRC (kHz) 110 109 108 107 2.7 V 106 3.3 V 105 4.0 V 4.5 V 5.5 V 104 103 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Figure 30-35. Watchdog Oscillator Frequency vs. VCC. 114 113 112 -40 °C 111 FRC (kHz) 110 109 25 °C 108 107 106 105 85 °C 104 103 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-36. Calibrated 8 MHz RC Oscillator Frequency vs. VCC. 8.2 85 °C 8.1 25 °C FRC (MHz) 8 -40 °C 7.9 7.8 7.7 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-37. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature. 8.2 8.15 5.0 V 8.1 FRC (MHz) 3.0 V 8.05 8 7.95 7.9 7.85 7.
Figure 30-38. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value. 14 85 °C 25 °C -40 °C 12 FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 30.1.12 Current Consumption of Peripheral Units Figure 30-39. ADC Current vs. VCC (AREF = AVCC). 400 -40 °C 25 °C 85 °C 350 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-40. Analog Comparator Current vs. VCC. 100 -40 °C 90 25 °C 85 °C 80 ICC (uA) 70 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-41. AREF External Reference Current vs. VCC. 180 85 °C 25 °C -40 °C 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-42. Brownout Detector Current vs. VCC. 70 60 ICC (uA) 50 40 30 85 °C 25 °C -40 °C 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-43. Programming Current vs. VCC. 6 -40 °C 5 25 °C ICC (mA) 4 3 85 °C 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P 30.1.13 Current Consumption in Reset and Reset Pulsewidth Figure 30-44. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz). 0.25 ICC (mA) 0.2 5.5 V 0.15 4.5 V 4.0 V 0.1 3.3 V 2.7 V 0.05 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-45. Reset Supply Current vs. Frequency (1 - 20 MHz). 4.5 4 5.5 V 3.5 ICC (mA) 3 4.5 V 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.
Figure 30-46. Minimum Reset Pulse width vs. VCC. 1800 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 25 °C -40 °C 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2 30.2.1 ATmega88P Typical Characteristics Active Supply Current Figure 30-47. Active Supply Current vs. Low Frequency (0.1-1.0 MHz). 1.4 5.5 V 1.2 1 ICC (mA) 4.5 V 0.8 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega48P/88P/168P Figure 30-48. Active Supply Current vs. Frequency (1-20 MHz). 18 5.5 V 16 14 ICC (mA) 12 4.5 V 10 4V 8 6 3.3 V 4 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-49. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.25 ICC (mA) 0.2 -40 °C 0.15 25 °C 85 °C 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-50. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 2 -40 °C 85 °C 1.8 1.6 25 °C ICC (mA) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-51. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 9 8 85 °C -40 °C 7 25 °C ICC (mA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P 30.2.2 Idle Supply Current Figure 30-52. Idle Supply Current vs. Low Frequency (0.1-1.0 MHz). 0.35 0.3 ICC (mA) 0.25 5.5 V 0.2 4.5 V 0.15 4.0 V 3.3 V 0.1 2.7 V 0.05 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-53. Idle Supply Current vs. Frequency (1-20 MHz). 5 4.5 4 5.5 V ICC (mA) 3.5 3 4.5 V 2.5 4V 2 1.5 3.3 V 1 2.7 V 0.5 1.
Figure 30-54. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.05 85 °C 0.045 ICC (mA) 0.04 0.035 25 °C 0.03 -40 °C 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-55. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 0.6 ICC (mA) -40 °C 0.5 85 °C 0.4 25 °C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-56. Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz). 3 2.5 85 °C -40 °C ICC (mA) 2 25 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
Table 30-4. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 30-47 on page 346 and Figure 30-48 on page 347) Additional Current consumption compared to Idle with external clock (see Figure 30-52 on page 349 and Figure 30-53 on page 349) PRTIM1 2.8% 17.0% PRTIM0 0.8% 4.6% PRSPI 3.0% 17.5% PRADC 2.9% 17.
ATmega48P/88P/168P Figure 30-58. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled). 9 85 °C -40 °C 25 °C 8 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.5 Power-save Supply Current Figure 30-59. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running). 1.6 25 °C 1.4 I CC(uA) 1.2 1.0 0.8 0.6 0.4 0.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
30.2.6 Standby Supply Current Figure 30-60. Standby Supply Current vs. Vcc (Watchdog Timer Disabled). 0.18 6MHz_res 6MHz_xtal 0.16 0.14 ICC (mA) 0.12 4MHz_res 4MHz_xtal 0.1 0.08 2MHz_res 2MHz_xtal 0.06 450kHz_res 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.7 Pin Pull-Up Figure 30-61. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V). 60 50 IOP (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega48P/88P/168P Figure 30-62. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V). 80 70 60 IOP (uA) 50 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 30-63. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V).
Figure 30-64. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V). 40 35 IRESET (uA) 30 25 20 15 10 25 °C -40 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 30-65. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V). 70 60 IRESET (uA) 50 40 30 20 25 °C -40 °C 85 °C 10 0 0 0.5 1 1.5 2 2.
ATmega48P/88P/168P Figure 30-66. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V). 120 100 IRESET (uA) IRESET (uA) 80 60 40 20 25 °C -40 °C 85 °C 0 0 1 2 3 4 5 6 VRESET (V) 30.2.8 Pin Driver Strength Figure 30-67. I/O Pin Output Voltage vs. Sink Current(VCC = 3 V). 1 85 °C 0.9 0.8 25 °C 0.7 -40 °C VOL (V) 0.6 0.5 0.4 0.3 0.2 0.
Figure 30-68. I/O Pin Output Voltage vs. Sink Current(VCC = 5 V). 0.7 85 °C 0.6 25 °C 0.5 VOL (V) -40 °C 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (mA) Figure 30-69. I/O Pin Output Voltage vs. Source Current(Vcc = 3 V). 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.
ATmega48P/88P/168P Figure 30-70. I/O Pin Output Voltage vs. Source Current(VCC = 5 V). 5 4.9 4.8 4.7 VOH (V) 4.6 4.5 -40 °C 25 °C 4.4 85 °C 4.3 4.2 4.1 4 0 5 10 15 20 25 IOH (mA) 30.2.9 Pin Threshold and Hysteresis Figure 30-71. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’). 4 3.5 Input Threshold (V) 3 -40 °C 25 °C 85 °C 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-72. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’). 2.5 85 °C 25 °C -40 °C Input Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-73. I/O Pin Input Hysteresis vs. VCC. 0.6 -40 °C 25 °C 85 °C Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-74. Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’). 2.5 -40 °C 25 °C 85 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-75. Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-76. Reset Pin Input Hysteresis vs. VCC. 0.6 Input Hysteresis (mV) 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.10 BOD Threshold Figure 30-77. BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V). 2.3 2.2 Threshold (V) 2.1 2 1.9 Rising Vcc 1.8 Falling Vcc 1.7 1.6 1.
ATmega48P/88P/168P Figure 30-78. BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V). 3 2.95 2.9 Threshold (V) 2.85 2.8 Rising Vcc 2.75 2.7 Falling Vcc 2.65 2.6 2.55 2.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 90 100 Temperature (°C) Figure 30-79. BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V). 4.5 4.45 4.4 Threshold (V) 4.35 Rising Vcc 4.3 4.25 Falling Vcc 4.2 4.15 4.1 4.
30.2.11 Internal Oscilllator Speed Figure 30-80. Watchdog Oscillator Frequency vs. Temperature. 112 110 108 FRC (kHz) 106 2.7 V 3.3 V 4.0 V 5.5 V 104 102 100 98 96 94 92 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-81. Watchdog Oscillator Frequency vs. VCC. 112 111 110 -40 °C FRC (kHz) 109 108 25 °C 107 106 105 104 103 85 °C 102 2.5 3 3.5 4 4.
ATmega48P/88P/168P Figure 30-82. Calibrated 8 MHz RC Oscillator Frequency vs. VCC. 8.3 85 °C 8.2 25 °C 8.1 FRC (MHz) -40 °C 8 7.9 7.8 7.7 7.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-83. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature. 8.4 8.3 5.0 V 8.2 FRC (MHz) 3.0 V 8.1 8 7.9 7.8 7.7 7.
Figure 30-84. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value. 14 85 °C 25 °C -40 °C 12 FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 30.2.12 Current Consumption of Peripheral Units Figure 30-85. ADC Current vs. VCC (AREF = AVCC). 400 350 -40 °C 25 °C 85 °C 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-86. Analog Comparator Current vs. VCC. 100 90 -40 °C 80 ICC (uA) 70 60 85 °C 25 °C 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-87. AREF External Reference Current vs. VCC. 160 85 °C 25 °C 140 -40 °C 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-88. Brownout Detector Current vs. VCC. 100 90 80 -40 °C ICC (uA) 70 60 50 25 °C 40 30 20 85 °C 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-89. Programming Current vs. VCC. 16 -40 °C 14 12 ICC (mA) 10 25 °C 85 °C 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P 30.2.13 Current Consumption in Reset and Reset Pulsewidth Figure 30-90. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz). 0.25 5.5 V 0.2 ICC (mA) 5.0 V 0.15 4.5 V 4.0 V 0.1 3.3 V 2.7 V 0.05 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-91. Reset Supply Current vs. Frequency (1 - 20 MHz). 4 5.5 V 3.5 3 4.5 V ICC (mA) 2.5 2 4V 1.5 3.3 V 1 2.7 V 0.5 1.
Figure 30-92. Minimum Reset Pulse width vs. VCC. 2000 1800 1600 Pulsewidth (ns) 1400 1200 1000 85 °C 25 °C -40 °C 800 600 400 200 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.3 30.3.1 ATmega168P Typical Characteristics Active Supply Current Figure 30-93. Active Supply Current vs. Low Frequency (0.1-1.0 MHz). 1.4 5.5 V 1.2 1 ICC (mA) 4.5 V 0.8 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega48P/88P/168P Figure 30-94. Active Supply Current vs. Frequency (1-20 MHz). 25 20 ICC (mA) 5.5 V 15 4.5 V 10 4.0 V 3.3 V 5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-95. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.18 85 °C 25 °C -40 °C 0.16 0.14 ICC (mA) 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-96. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 1.8 1.6 85 °C 25 °C -40 °C 1.4 ICC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-97. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz). 9 85 °C 25 °C -40 °C 8 7 ICC (mA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P 30.3.2 Idle Supply Current Figure 30-98. Idle Supply Current vs. Low Frequency (0.1-1.0 MHz). 0.3 0.25 5.5 V 5.0 V ICC (mA) 0.2 4.5 V 0.15 4.0 V 3.3 V 0.1 2.7 V 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-99. Idle Supply Current vs. Frequency (1-20 MHz). 5 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC (mA) 3 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.
Figure 30-100.Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz). 0.05 85 °C 0.045 0.04 25 °C 0.035 -40 °C ICC (mA) 0.03 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-101.Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz). 0.5 85 °C 25 °C -40 °C 0.45 0.4 0.35 ICC (mA) 0.3 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-102.Idle Supply Current vs. Vcc (Internal RC Oscillator, 8 MHz). 3 2.5 85 °C 25 °C -40 °C ICC (mA) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.3.3 Supply Current of IO Modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
Table 30-6. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 30-93 on page 370 and Figure 30-94 on page 371) Additional Current consumption compared to Idle with external clock (see Figure 30-98 on page 373 and Figure 30-99 on page 373) PRUSART0 1.9% 8.5% PRTWI 3.4% 15.6% PRTIM2 3.6% 16.5% PRTIM1 3.4% 15.2% PRTIM0 0.8% 3.7% PRSPI 3.5% 15.8% PRADC 3.2% 14.
ATmega48P/88P/168P Figure 30-104.Power-Down Supply Current vs. VCC (Watchdog Timer Enabled). 9 85 °C -40 °C 25 °C 8 7 ICC (uA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.3.5 Power-save Supply Current Figure 30-105.Power-Save Supply Current vs. VCC (Watchdog Timer Disabled and 32 kHz Crystal Oscillator Running). 1.6 25 °C 1.4 1.2 ICC (uA) 1.0 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
30.3.6 Standby Supply Current Figure 30-106.Standby Supply Current vs. Vcc (Watchdog Timer Disabled). 0.2 6MHz_xtal 0.18 0.16 6MHz_res 0.14 4MHz_xtal 4MHz_res ICC (mA) 0.12 0.1 2MHz_xtal 2MHz_res 0.08 0.06 1MHz_res 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.3.7 Pin Pull-Up Figure 30-107.I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V). 60 50 25 °C -40 °C IOP (uA) 40 85 °C 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega48P/88P/168P Figure 30-108.I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V). 90 80 25 °C 70 IOP (uA) 60 -40 °C 85 °C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 30-109.I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V).
Figure 30-110.Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V). 40 35 30 25 °C -40 °C IRESET (uA) 25 85 °C 20 15 10 5 0 0 0.2 0.4 0.8 0.6 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 30-111.Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V). 70 60 IRESET (uA) 50 25 °C -40 °C 40 85 °C 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega48P/88P/168P Figure 30-112.Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V). 120 100 25 °C -40 °C IRESET (uA) 80 85 °C 60 40 20 0 0 1 2 3 4 5 6 VRESET (V) 30.3.8 Pin Driver Strength Figure 30-113.I/O Pin Output Voltage vs. Sink Current(VCC = 3 V). 1.2 1 85 °C 0.8 VOL (V) 25 °C 0.6 -40 °C 0.4 0.
Figure 30-114.I/O Pin Output Voltage vs. Sink Current(VCC = 5 V). 0.7 85 °C 0.6 25 °C 0.5 VOL (V) -40 °C 0.4 0.3 0.2 0.1 0 0 5 10 15 20 25 IOL (mA) Figure 30-115.I/O Pin Output Voltage vs. Source Current(Vcc = 3 V). 3.5 3 VOH (V) 2.5 -40 °C 25 °C 85 °C 2 1.5 1 0.
ATmega48P/88P/168P Figure 30-116.I/O Pin Output Voltage vs. Source Current(VCC = 5 V). 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 4.5 -40 °C 25 °C 4.4 85 °C 4.3 4.2 0 5 10 15 20 25 IOH (mA) 30.3.9 Pin Threshold and Hysteresis Figure 30-117.I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’). , 3.5 85 °C 25 °C -40 °C 3 Threshold (V) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-118.I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’). 85 °C 25 °C -40 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-119.I/O Pin Input Hysteresis vs. VCC. 0.6 85 °C 25 °C -40 °C Input Hysteresis (mV) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-120.Reset Input Threshold Voltage vs. VCC (VIH, I/O Pin read as ‘1’). 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-121.Reset Input Threshold Voltage vs. VCC (VIL, I/O Pin read as ‘0’). 2.5 -40 °C 85 °C 25 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-122.Reset Pin Input Hysteresis vs. VCC. 0.6 0.5 Input Hysteresis (mV) -4 0°C 0.4 0.3 2 5°C 0.2 0.1 8 5°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.3.10 BOD Threshold Figure 30-123.BOD Thresholds vs. Temperature (BODLEVEL is 1.8 V). 1.9 1.88 1.86 Threshold (V) 1.84 Rising Vcc 1.82 1.8 Falling Vcc 1.78 1.76 1.74 1.72 1.
ATmega48P/88P/168P Figure 30-124.BOD Thresholds vs. Temperature (BODLEVEL is 2.7 V). 3 2.95 2.9 Threshold (V) 2.85 2.8 Rising Vcc 2.75 2.7 2.65 Falling Vcc 2.6 2.55 2,5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 90 100 Temperature (°C) Figure 30-125.BOD Thresholds vs. Temperature (BODLEVEL is 4.3 V). 4.5 4.45 4.4 4.35 Threshold (V) Rising Vcc 4.3 4.25 Falling Vcc 4.2 4.15 4.1 4.
30.3.11 Internal Oscilllator Speed Figure 30-126.Watchdog Oscillator Frequency vs. Temperature. 120 118 116 FRC (kHz) 114 2.7 V 112 3.3 V 110 5.0 V 108 106 104 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (°C) Figure 30-127.Watchdog Oscillator Frequency vs. VCC. 120 119 118 117 FRC (kHz) 116 25 °C 115 114 113 112 111 85 °C 110 109 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-128.Calibrated 8 MHz RC Oscillator Frequency vs. VCC. 8.1 85 °C 8.05 25 °C FRC (MHz) 8 7.95 7.9 7.85 7.8 2 2.5 3 3.5 4 4.5 5 5.5 (V) Figure 30-129.Calibrated 8 MHz RC Oscillator Frequency vs. Temperature. 8.15 5.5 V 8.1 FRC (MHz) 8.05 8 2.7 V 7.95 7.9 7.85 1.8 V 7.
Figure 30-130.Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value. 14 25 °C 85 °C 12 FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL (X1) 30.3.12 Current Consumption of Peripheral Units Figure 30-131.ADC Current vs. VCC (AREF = AVCC). 400 350 25 °C 300 ICC (uA) 85 °C 250 -40 °C 200 150 100 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P Figure 30-132.Analog Comparator Current vs. VCC. 95 -40 °C 25 °C 85 °C 85 ICC (uA) 75 65 55 45 35 25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-133.AREF External Reference Current vs. VCC. 180 25 °C 85 °C -40 °C 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 30-134.Brownout Detector Current vs. VCC. 28 26 25 °C 85 °C 24 22 ICC (uA) -40 °C 20 18 16 14 12 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-135.Programming Current vs. VCC. 14 -40 °C 12 ICC (mA) 10 85 °C 25 °C 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P 30.3.13 Current Consumption in Reset and Reset Pulsewidth Figure 30-136.Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz). 0.2 5.5 V 0.18 0.16 5.0 V 0.14 4.5 V ICC (mA) 0.12 4.0 V 0.1 3.3 V 0.08 2.7 V 0.06 1.8 V 0.04 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-137.Reset Supply Current vs. Frequency (1 - 20 MHz). 4 5.5 V 3.5 5.0 V 3 4.5 V ICC (mA) 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.
Figure 30-138.Minimum Reset Pulse width vs. VCC. 1800 1600 1400 Pulsewidth (ns) 1200 1000 800 600 400 85 °C 200 25 °C -40 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega48P/88P/168P 31.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 194 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 193 396 Page (0xBF) Reserved – – – – – – – – (0xBE) Reserved – – – – – – – – (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 – 242 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 239 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWS7 TWS6
ATmega48P/88P/168P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x7F) DIDR1 – – – – – – AIN1D AIN0D 247 (0x7E) DIDR0 – – ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 264 (0x7D) Reserved – – – – – – – – (0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 260 (0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 263 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH ADC Data Register High byte Page 261 263 (0x78)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1D (0x3D) EIMSK – – – – – – INT1 INT0 Page 70 0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 70 0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF0 0x1A (0x3A) Reserved – – – – – – – – 0x19 (0x39) Reserved – – – – – – – – 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) TIFR2 – – – – – OCF2B OCF2A TOV2 161 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 138 0x15 (0
ATmega48P/88P/168P 32.
Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V
ATmega48P/88P/168P Mnemonics POP Operands Rd Description Pop Register from Stack Operation Rd ← STACK Flags #Clocks None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/timer) For On-chip Debug Only None None 1 N/A Note: 1. These instructions are only available in ATmega168P.
33. Ordering Information 33.1 ATmega48P Speed (MHz) 10(3) 20(3) Note: Ordering Code(2) Package(1) 1.8 - 5.5 ATmega48PV-10AU ATmega48PV-10AUR(4) ATmega48PV-10MMU ATmega48PV-10MMUR(4) ATmega48PV-10MU ATmega48PV-10MUR(4) ATmega48PV-10PU 32A 32A 28M1 28M1 32M1-A 32M1-A 28P3 2.7 - 5.
ATmega48P/88P/168P 33.2 ATmega88P Speed (MHz) 10(3) 20(3) Note: Ordering Code(2) Package(1) 1.8 - 5.5 ATmega88PV-10AU ATmega88PV-10AUR(4) ATmega88PV-10MU ATmega88PV-10MUR(4) ATmega88PV-10PU 32A 32A 32M1-A 32M1-A 28P3 2.7 - 5.5 ATmega88P-20AU ATmega88P-20AUR(4) ATmega88P-20MU ATmega88P-20MUR(4) ATmega88P-20PU 32A 32A 32M1-A 32M1-A 28P3 Power Supply (V) Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form.
33.3 ATmega168P Speed (MHz)(3) 10 20 Note: Ordering Code(2) Package(1) 1.8 - 5.5 ATmega168PV-10AU ATmega168PV-10AUR(4) ATmega168PV-10MU ATmega168PV-10MUR(4) ATmega168PV-10PU 32A 32A 32M1-A 32M1-A 28P3 2.7 - 5.5 ATmega168P-20AU ATmega168P-20AUR(4) ATmega168P-20MU ATmega168P-20MUR(4) ATmega168P-20PU 32A 32A 32M1-A 32M1-A 28P3 Power Supply (V) Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form.
ATmega48P/88P/168P 34. Packaging Information 34.1 32A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 SYMBOL Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion.
34.2 28M1 D C 1 2 Pin 1 ID 3 E SIDE VIEW A1 TOP VIEW A y D2 K 1 0.45 2 R 0.20 3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 C L e 0.4 Ref (4x) Note: 0.20 REF D 3.95 4.00 4.05 D2 2.35 2.40 2.45 E 3.95 4.00 4.05 E2 2.35 2.40 2.45 e BOTTOM VIEW The terminal #1 ID is a Laser-marked Feature. NOTE 0.45 L 0.35 0.40 0.45 y 0.00 – 0.08 K 0.
ATmega48P/88P/168P 34.3 32M1-A D D1 1 2 3 0 Pin 1 ID E1 SIDE VIEW E TOP VIEW A3 A2 A1 A K 0.08 C P D2 1 2 3 P Pin #1 Notch (0.20 R) K e SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 E2 b COMMON DIMENSIONS (Unit of Measure = mm) L BOTTOM VIEW 0.20 REF b 0.18 0.23 0.30 D 4.90 5.00 5.10 D1 4.70 4.75 4.80 D2 2.95 3.10 3.25 E 4.90 5.00 5.10 E1 4.70 4.75 4.80 E2 2.95 3.10 3.25 e Note: JEDEC Standard MO-220, Fig.
34.4 28P3 D PIN 1 E1 A SEATING PLANE L B2 B1 B A1 (4 PLACES) e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF SYMBOL eB Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 4.5724 A1 0.508 – – D 34.544 – 34.798 E 7.620 – 8.255 E1 7.112 – 7.493 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.
ATmega48P/88P/168P 35. Errata 35.1 Errata ATmega48P The revision letter in this section refers to the revision of the ATmega48P device. 35.1.1 Rev. C No known errata. 35.1.2 Rev. B No known errata. 35.1.3 Rev. A Not Sampled. 35.2 Errata ATmega88P The revision letter in this section refers to the revision of the ATmega88P device. 35.2.1 Rev. C Not sampled. 35.2.2 Rev. B No known errata. 35.2.3 Rev. A No known errata. 35.
36. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 36.2 Rev. 8025M-06/11 1. 2. Added Atmel QTouch Library Support and QTouch Sensing Capability Features. Updated “Ordering Information” to include Tape and Reel devices. 3. Updated the datasheet with Atmel new style guide. Rev. 8025L-07/10 1. 2. 36.3 Rev. 8025K-10/09 1. 2. 36.
ATmega48P/88P/168P 36.7 Rev. 8025G-01/09 1 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 36.8 Rev. 8025F-08/08 1. 2. 36.9 ATmega48P/88P not recommended for new designs. Updated the footnote Note1 of the Table 9-3 on page 30. Updated the Table 9-5 on page 31 by removing a footnote Note1. Updated the Table 9-11 on page 34 by removing a footnote Note1. Updated the footnote Note1 of the Table 9-13 on page 35.
36.10 Rev. 8025D-03/08 1. 2. 3. 4. Updated figures in ”Speed Grades” on page 312. Updated note in Table 29-4 in ”System and Reset Characteristics” on page 314. Ordering codes for ”Packaging Information” on page 405 updated. - ATmega328P is offered in 20 MHz option only. Added Errata for ATmega328P rev. B, ”” on page 409. 36.11 Rev. 8025C-01/08 1.
ATmega48P/88P/168P Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1Pin Descriptions ........................................................................................................3 2 Overview ................................................................................................... 4 2.
9.6Calibrated Internal RC Oscillator .............................................................................34 9.7128 kHz Internal Oscillator ......................................................................................35 9.8External Clock .........................................................................................................35 9.9Clock Output Buffer .................................................................................................36 9.
ATmega48P/88P/168P 13.1Pin Change Interrupt Timing .................................................................................68 13.2Register Description ..............................................................................................69 14 I/O-Ports .................................................................................................. 73 14.1Overview ...............................................................................................................73 14.
18 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 142 18.1Features ..............................................................................................................142 18.2Overview .............................................................................................................142 18.3Timer/Counter Clock Sources .............................................................................143 18.4Counter Unit ..........................................................
ATmega48P/88P/168P 21.5Frame Formats ....................................................................................................204 21.6Data Transfer ......................................................................................................206 21.7AVR USART MSPIM vs. AVR SPI ......................................................................208 21.8Register Description ............................................................................................
26 Self-Programming the Flash, ATmega48P ........................................ 267 26.1Overview .............................................................................................................267 26.2Addressing the Flash During Self-Programming .................................................268 26.3Register Description’ ...........................................................................................
ATmega48P/88P/168P 30.1ATmega48P Typical Characteristics ...................................................................322 30.2ATmega88P Typical Characteristics ...................................................................346 30.3ATmega168P Typical Characteristics .................................................................370 31 Register Summary ............................................................................... 395 32 Instruction Set Summary ...................................
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