Datasheet

373
7674F–AVR–09/09
ATmega164P/324P/644P
19.7 Transmission Modes .....................................................................................221
19.8 Multi-master Systems and Arbitration ............................................................234
19.9 Register Description ......................................................................................235
20 AC - Analog Comparator ..................................................................... 240
20.1 Overview ........................................................................................................240
20.2 Analog Comparator Multiplexed Input ...........................................................240
20.3 Register Description ......................................................................................241
21 ADC - Analog-to-digital Converter ..................................................... 243
21.1 Features ........................................................................................................243
21.2 Overview ........................................................................................................243
21.3 Operation .......................................................................................................244
21.4 Starting a Conversion ....................................................................................245
21.5 Prescaling and Conversion Timing ................................................................246
21.6 Changing Channel or Reference Selection ...................................................249
21.7 ADC Noise Canceler .....................................................................................251
21.8 ADC Conversion Result .................................................................................256
21.9 Register Description ......................................................................................258
22 JTAG Interface and On-chip Debug System ..................................... 263
22.1 Features ........................................................................................................263
22.2 Overview ........................................................................................................263
22.3 TAP – Test Access Port ................................................................................264
22.4 TAP Controller ...............................................................................................265
22.5 Using the Boundary-scan Chain ....................................................................266
22.6 Using the On-chip Debug System .................................................................266
22.7 On-chip Debug Specific JTAG Instructions ...................................................267
22.8 Using the JTAG Programming Capabilities ...................................................268
22.9 Bibliography ...................................................................................................268
22.10 Register Description ......................................................................................268
23 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 269
23.1 Features ........................................................................................................269
23.2 Overview ........................................................................................................269
23.3 Data Registers ...............................................................................................270
23.4 Boundary-scan Specific JTAG Instructions ...................................................271
23.5 Boundary-scan Chain ....................................................................................272
23.6 ATmega164P/324P/644P Boundary-scan Order ..........................................275