Datasheet

335
7674F–AVR–09/09
ATmega164P/324P/644P
Notes: 1. Values indicated represent typical data from design simulation.
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega164P/324P/644P Two-wire Serial Interface operation. Other devices connected to the
Two-wire Serial Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATmega164P/324P/644P Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK
must be greater than 6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
7. The actual low period generated by the ATmega164P/324P/644P Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low
time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATmega164P/324P/644P devices con-
nected to the bus may communicate at full speed (400 kHz) with other ATmega164P/324P/644P devices, as well as any
other device with a proper tLOW acceptance margin.
Figure 26-5. 2-wire Serial Bus Timing
t
HIGH
High period of the SCL clock
f
SCL
≤ 100 kHz 4.0 – µs
f
SCL
> 100 kHz 0.6 – µs
t
SU;STA
Set-up time for a repeated START condition
f
SCL
≤ 100 kHz 4.7 – µs
f
SCL
> 100 kHz 0.6 – µs
t
HD;DAT
Data hold time
f
SCL
≤ 100 kHz 0 3.45 µs
f
SCL
> 100 kHz 0 0.9 µs
t
SU;DAT
Data setup time
f
SCL
≤ 100 kHz 250 – ns
f
SCL
> 100 kHz 100 – ns
t
SU;STO
Setup time for STOP condition
f
SCL
≤ 100 kHz 4.0 – µs
f
SCL
> 100 kHz 0.6 – µs
t
BUF
Bus free time between a STOP and START
condition
f
SCL
≤ 100 kHz 4.7 – µs
f
SCL
> 100 kHz 1.3 – µs
Table 26-7. 2-wire Serial Bus Requirements
(1)
(Continued)
Symbol Parameter
Condition Min Max Units
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r