Datasheet

300
7674F–AVR–09/09
ATmega164P/324P/644P
25.6 Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits in the ATmega164P/324P/644P. Pulses are
assumed to be at least 250 ns unless otherwise noted.
25.6.1 Signal Names
In this section, some pins of the ATmega164P/324P/644P are referenced by signal names
describing their functionality during parallel programming, see Figure 25-1 on page 300 and Fig-
ure 25-9 on page 300. Pins not described in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.
The bit coding is shown in Table 25-12 on page 301.
When pulsing WR
or OE, the command loaded determines the action executed. The different
commands are shown in Table 25-13 on page 301.
Figure 25-1. Parallel Programming
(1)
Note: 1. Unused Pins should be left floating.
Table 25-9. Pin Name Mapping
Signal Name in
Programming Mode Pin Name I/O Function
RDY/BSY
PD1 O
0: Device is busy programming, 1: Device is ready for
new command.
OE PD2 I Output Enable (Active low).
WR
PD3 I Write Pulse (Active low).
BS1 PD4 I Byte Select 1.
XA0 PD5 I XTAL Action Bit 0
XA1 PD6 I XTAL Action Bit 1
VCC
+5V
GND
XTAL1
PD1
PD2
PD3
PD4
PD5
PD6
PB7 - PB0 DATA
RESET
PD7
+12 V
BS1
XA0
XA1
OE
RDY/BSY
PAGEL
PA0
WR
BS2
AVCC
+5V