Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories – 16/32/64K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System P
1. Pin Configurations Figure 1-1.
ATmega164P/324P/644P 2. Overview The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PA7..0 PB7..
The ATmega164P/324P/644P provides the following features: 16/32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1/2/4K bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Inte
ATmega164P/324P/644P 2.2.1 Automotive Quality Grade The ATmega164P/324P/644P have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATmega164P/324P/644P have been verified during regular product qualification as per AEC-Q100 grade 1 (–40°C to +125°C). Table 2-2.
2.3.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega164P/324P/644P 3. Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr.
4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. The code examples assume that the part specific header file is included before compilation.
ATmega164P/324P/644P 5. AVR CPU Core 5.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 5-1.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATmega164P/324P/644P 5.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 5.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega164P/324P/644P 5.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5-3. Figure 5-3.
5.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) – – – SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write Initial Value 5.6 R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 Instruction Execution Timing This section describes the general access timing concepts for instruction execution.
ATmega164P/324P/644P Figure 5-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 5.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
ATmega164P/324P/644P 5.7.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles.
6. AVR Memories 6.1 Overview This section describes the different memories in the ATmega164P/324P/644P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega164P/324P/644P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 6.2 In-System Reprogrammable Flash Program Memory The ATmega164P/324P/644P contains 16/32/64K bytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega164P/324P/644P Figure 6-1. Program Memory Map Program Memory 0x0000 Application Flash Section Boot Flash Section 0x1FFF 6.3 SRAM Data Memory Figure 6-2 shows how the ATmega164P/324P/644P SRAM Memory is organized. The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions.
The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 12. Figure 6-2. Data Memory Map Data Memory $0000 - $001F $0020 - $005F $0060 - $00FF $0100 32 Registers 64 I/O Registers 160 Ext I/O Reg. Internal SRAM (1024/2048/4096 x 8) $10FF 6.3.
ATmega164P/324P/644P 6.4 EEPROM Data Memory The ATmega164P/324P/644P contains 512B/1K/2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
6.5 I/O Memory The I/O space definition of the ATmega164P/324P/644P is shown in “Register Summary” on page 356. All ATmega164P/324P/644P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions.
ATmega164P/324P/644P 6.6 6.6.
While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 6-1. EEPROM Mode Bits EEPM1 EEPM0 Programming Time 0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Operation Reserved for future use • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
ATmega164P/324P/644P When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM.
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
ATmega164P/324P/644P The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
6.6.4 GPIOR2 – General Purpose I/O Register 2 Bit 6.6.
ATmega164P/324P/644P 7. System Clock and Clock Options 7.1 Clock Systems and their Distribution Figure 7-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 41. The clock systems are detailed below. Figure 7-1.
7.1.3 Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 7.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 7.1.
ATmega164P/324P/644P 7.2.2 Clock Startup Sequence Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be considered stable. To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is released by all other reset sources. “On-chip Debug System” on page 45 describes the start conditions for the internal reset.
Figure 7-2. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND 7.3 Low Power Crystal Oscillator This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, refer to the “Full Swing Crystal Oscillator” on page 33.
ATmega164P/324P/644P Table 7-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 Ceramic resonator, fast rising power 258 CK 14CK + 4.1 ms(1) 0 00 Ceramic resonator, slowly rising power 258 CK 14CK + 65 ms(1) 0 01 Ceramic resonator, BOD enabled 1K CK 14CK(2) 0 10 Ceramic resonator, fast rising power 1K CK 14CK + 4.
Table 7-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) CKSEL0 SUT1..0 Ceramic resonator, fast rising power 258 CK 14CK + 4.1 ms(1) 0 00 Ceramic resonator, slowly rising power 258 CK 14CK + 65 ms(1) 0 01 Ceramic resonator, BOD enabled 1K CK 14CK(2) 0 10 Ceramic resonator, fast rising power 1K CK 14CK + 4.
ATmega164P/324P/644P Figure 7-3. Crystal Oscillator Connections TOSC2 TOSC1 Table 7-8. Low-frequency Crystal Oscillator Internal load Capacitance Min. (pF) Typ. (pF) Max. (pF) TBD 8.0 TBD Crystals specifying load capacitance (CL) higher than 8.0 pF, require external capacitors applied as described in Figure 7-2 on page 32. To find suitable load capacitance for a 32.768 kHz crysal, please consult the crystal datasheet.
7.6 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the the user. See Table 26-2 on page 331 and Section 27.7 “Internal Oscillator Speed” on page 350 for more details. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 38 for more details.
ATmega164P/324P/644P 7.7 128 kHz Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25° C. This clock may be select as the system clock by programming the CKSEL Fuses to “0011” as shown in Table 7-12. Table 7-12. Note: 128 kHz Internal Oscillator Operating Modes Nominal Frequency CKSEL3..0 128 kHz 0011 1. The frequency is preliminary value. Actual value is TBD.
Table 7-15. Start-up Times for the External Clock Selection Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1..0 BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms 10 Power Conditions Reserved 11 When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU.
ATmega164P/324P/644P When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency.
7.12.2 CLKPR – Clock Prescale Register Bit 7 6 5 4 3 2 1 0 CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 (0x61) CLKPR See Bit Description • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
ATmega164P/324P/644P 8. Power Management and Sleep Modes 8.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
8.3 BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 25-3 on page 297, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 8-1 on page 41. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode.
ATmega164P/324P/644P 8.6 Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2-wire Serial Interface, and the Watchdog continue operating (if enabled).
8.10 Power Reduction Register The Power Reduction Register(PRR), see “PRR – Power Reduction Register” on page 47, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
ATmega164P/324P/644P 8.11.5 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Interrupts” on page 60 for details on how to configure the Watchdog Timer. 8.11.
8.12 8.12.1 Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 8-2. Table 8-2.
ATmega164P/324P/644P 8.12.2 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 6 – BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 8-1 on page 41. Writing to the BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR.
• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation. • Bit 1 - PRUSART0: Power Reduction USART0 Writing a logic one to this bit shuts down the USART0 by stopping the clock to the module. When waking up the USART0 again, the USART0 should be reinitialized to ensure proper operation.
ATmega164P/324P/644P 9. System Control and Reset 9.0.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 9-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 9.0.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 332.
ATmega164P/324P/644P Figure 1. MCU Start-up, RESET Tied to VCC V CCRR VCC VPORMAX VPORMIN RESET VRST tTOUT TIME-OUT INTERNAL RESET Figure 2. MCU Start-up, RESET Extended Externally VCC VRST RESET tTOUT TIME-OUT INTERNAL RESET Table 1. Power On Reset Specifications Symbol VPOT Min Typ Max Units Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.7 V Power-on Reset Threshold Voltage (falling)(1) 0.8 1.3 1.6 V 0.4 V VPORMAX VCC Max.
Figure 9-2. External Reset During Operation CC 9.0.5 Brown-out Detection ATmega164P/324P/644P has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
ATmega164P/324P/644P Figure 9-4. Watchdog Reset During Operation CC CK 9.1 Internal Voltage Reference ATmega164P/324P/644P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 9.1.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in “System and Reset Characteristics” on page 332.
9.2 9.2.1 Watchdog Timer Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 9.2.2 Overview ATmega164P/324P/644P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator.
ATmega164P/324P/644P 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watchdog Timer.
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.
ATmega164P/324P/644P 9.3 9.3.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x34 (0x54) – – – JTRF WDRF BORF EXTRF PORF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 MCUSR See Bit Description • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
9.3.2 WDTCSR – Watchdog Timer Control Register Bit 7 6 5 4 3 2 1 0 (0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCSR • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
ATmega164P/324P/644P • Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 9-2 on page 59. . Table 9-2. Watchdog Timer Prescale Select WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 5.
10. Interrupts 10.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega164P/324P/644P. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 15. 10.2 Interrupt Vectors in ATmega164P/324P/644P Table 10-1. Vector No.
ATmega164P/324P/644P Table 10-1. Vector No. Reset and Interrupt Vectors (Continued) Program Address(2) Source Interrupt Definition 28 $0036 SPM_READY Store Program Memory Ready 29 $0038 USART1_RX USART1 Rx Complete 30 $003A USART1_UDRE USART1 Data Register Empty 31 $003C USART1_TX USART1 Tx Complete Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Memory Programming” on page 296. 2.
0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 0x0034 0x0036 0x0038 0x003A 0x003C ; 0x003E RESET: jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp TIM0_COMPB TIM0_OVF SPI_STC USART0_RXC USART0_UDRE USART0_TXC ANA_COMP ADC EE_RDY TWI SPM_RDY USART1_RXC USART1_UDRE USART1_TXC ; ; ; ; ; ; ; ; ; ; ; ; ; ; ldi r16, high(RAMEND) SPH,r16 ; Main program start 0x003F out 0x0040 ldi 0x0041 0x0042 0x0043 ... out sei ... ...
ATmega164P/324P/644P When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org 0x0002 0x00002 jmp EXT_INT0 ; IRQ0 Handler 0x00004 jmp EXT_INT1 ; IRQ1 Handler ... ... ... ; 0x00036 jmp SPM_RDY ; SPM Ready Handler ; .
10.3 10.3.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash.
ATmega164P/324P/644P Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1<
11. External Interrupts 11.1 Overview The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as outputs. This feature provides a way of generating a software interrupt.
ATmega164P/324P/644P If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed.
11.2.4 PCICR – Pin Change Interrupt Control Register Bit 7 6 5 4 3 2 1 0 (0x68) – – – – PCIE3 PCIE2 PCIE1 PCIE0 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCICR • Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 3 is enabled. Any change on any enabled PCINT31..24 pin will cause an interrupt.
ATmega164P/324P/644P • Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..
11.2.9 PCMSK0 – Pin Change Mask Register 0 Bit 7 6 5 4 3 2 1 0 (0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK0 • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7..0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin.
ATmega164P/324P/644P 12. I/O-Ports 12.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 12.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 12-2.
ATmega164P/324P/644P If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 12.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 12.2.
Figure 12-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega164P/324P/644P Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
12.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega164P/324P/644P 12.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 12-5 shows how the port pin control signals from the simplified Figure 12-2 on page 72 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 12-5.
Table 12-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 12-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 12-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATmega164P/324P/644P 12.3.1 Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. Table 12-3.
Table 12-4 on page 80 and Table 12-5 on page 80 relates the alternate functions of Port A to the overriding signals shown in Figure 12-5 on page 77. Table 12-4.
ATmega164P/324P/644P 12.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 12-6. Table 12-6.
• MOSI/PCINT13 – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. PCINT13, Pin Change Interrupt source 13: The PB5 pin can serve as an external interrupt source.
ATmega164P/324P/644P • T0/XCK0/PCINT8, Bit 0 T0, Timer/Counter0 counter source. XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source.
12.3.3 Alternate Functions of Port C The Port C alternate function is as follows: Table 12-9.
ATmega164P/324P/644P • TMS/PCINT19 – Port C, Bit 3 TMS, JTAG Test Mode Select. PCINT19, Pin Change Interrupt source 19: The PC3 pin can serve as an external interrupt source. • TCK/PCINT18 – Port C, Bit 2 TCK, JTAG Test Clock. PCINT18, Pin Change Interrupt source 18: The PC2 pin can serve as an external interrupt source. • SDA/PCINT17 – Port C, Bit 1 SDA, 2-wire Serial Bus Data Input/Output Line. PCINT17, Pin Change Interrupt source 17: The PC1 pin can serve as an external interrupt source.
Table 12-11. Overriding Signals for Alternate Functions in PC3:PC0 12.3.
ATmega164P/324P/644P The alternate pin configuration is as follows: • OC2A/PCINT31 – Port D, Bit 7 OC2A, Output Compare Match A output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDD7 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function. PCINT31, Pin Change Interrupt Source 31:The PD7 pin can serve as an external interrupt source.
• INT0/RXD1/PCINT26 – Port D, Bit 2 INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU. RXD1, RXD0, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit. PCINT26, Pin Change Interrupt Source 26: The PD2 pin can serve as an external interrupt source.
ATmega164P/324P/644P Table 12-14.
Register Description 12.3.5 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATmega164P/324P/644P 12.3.12 PORTC – Port C Data Register Bit 12.3.13 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 12.3.
13. 8-bit Timer/Counter0 with PWM 13.1 Features • • • • • • • 13.2 Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support.
ATmega164P/324P/644P The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
ATmega164P/324P/644P Figure 13-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
13.5.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting.
ATmega164P/324P/644P The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 103. 13.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
Figure 13-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega164P/324P/644P PWM mode is shown in Figure 13-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 13-6.
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 13.7.
ATmega164P/324P/644P In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 13-4 on page 104).
Figure 13-9 shows the same timing data, but with the prescaler enabled. Figure 13-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 13-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 13-10.
ATmega164P/324P/644P 13.9 13.9.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
Table 13-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. Note: Description 1. A special case occurs when OCR0A equals TOP and COM0A1 is set.
ATmega164P/324P/644P Table 13-7 on page 105 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 13-7. COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting. Note: Description 1.
13.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
ATmega164P/324P/644P • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 13-9. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge.
13.9.5 OCR0B – Output Compare Register B Bit 7 6 5 0x28 (0x48) 4 3 2 1 0 OCR0B[7:0] OCR0B Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin. 13.9.
ATmega164P/324P/644P • Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to the flag.
14. 16-bit Timer/Counter1 with PWM 14.1 Features • • • • • • • • • • • 14.2 True 16-bit Design (i.e.
ATmega164P/324P/644P Figure 14-1. 16-bit Timer/Counter Block Diagram(Note:) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 14.2.
See “Output Compare Units” on page 119.. The compare match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See “AC - Analog Comparator” on page 240.
ATmega164P/324P/644P Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. The example code assumes that the part specific header file is included.
The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
ATmega164P/324P/644P The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
14.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 14-2 shows a block diagram of the counter and its surroundings. Figure 14-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega164P/324P/644P The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 14.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit.
The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 112.
ATmega164P/324P/644P Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 14.
The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega164P/324P/644P 14.8 Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 14-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
14.8.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 14-2 on page 132.
ATmega164P/324P/644P The timing diagram for the CTC mode is shown in Figure 14-6. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 14-6.
Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost.
ATmega164P/324P/644P The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will miss the compare match at the TOP value.
In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA.
ATmega164P/324P/644P When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Registers are written.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 14-8 and Figure 14-9). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
ATmega164P/324P/644P As Figure 14-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA.
Figure 14-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 14-11 shows the same timing data, but with the prescaler enabled. Figure 14-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 14-12 shows the count sequence close to TOP in various modes.
ATmega164P/324P/644P Figure 14-12. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx New OCRnx Value Old OCRnx Value (Update at TOP) Figure 14-13 shows the same timing data, but with the prescaler enabled. Figure 14-13.
The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the I/O pin it is connected to.
ATmega164P/324P/644P Table 14-4 on page 133 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 14-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COMnA1/COMnB1 COMnA0/COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 9 or 11: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation).
Waveform Generation Mode Bit Description(1) Table 14-5.
ATmega164P/324P/644P When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written. • Bit 4:3 – WGMn3:2: Waveform Generation Mode See TCCRnA Register description.
A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 14.11.
ATmega164P/324P/644P 14.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
14.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega164P/324P/644P, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin.
ATmega164P/324P/644P 15. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 15.1 Features • • • • • • • 15.
15.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section.
ATmega164P/324P/644P 15.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surrounding environment. Figure 15-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1.
15.5 Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed.
ATmega164P/324P/644P 15.5.2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 15.5.
Figure 15-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx Waveform Generator D Q 1 OCnx DATA BUS D 0 OCnx Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATmega164P/324P/644P 15.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
ATmega164P/324P/644P Figure 15-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.
15.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when MGM22:0 = 5.
ATmega164P/324P/644P The PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x Register at compare match between OCR2x and TCNT2 when the counter decrements.
Figure 15-9 on page 150 shows the same timing data, but with the prescaler enabled. Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 15-10 on page 150 shows the setting of OCF2A in all modes except CTC mode. Figure 15-10.
ATmega164P/324P/644P Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx 15.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted.
• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up.
ATmega164P/324P/644P 15.10 Timer/Counter Prescaler Figure 15-12. Prescaler for Timer/Counter2 clkT2S PSRASY clkT2S/1024 clkT2S/256 clkT2S/128 clkT2S/8 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear TOSC1 clkT2S/32 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. Table 15-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 15-2. Compare Output Mode, non-PWM Mode COM2A1 COM2A0 Description 0 0 Normal port operation, OC0A disconnected.
ATmega164P/324P/644P When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. Table 15-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM). Table 15-5. Compare Output Mode, non-PWM Mode COM2B1 COM2B0 Description 0 0 Normal port operation, OC2B disconnected.
• Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 15-8. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 145). Table 15-8.
ATmega164P/324P/644P • Bit 6 – FOC2B: Force Output Compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a strobe.
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. 15.11.4 OCR2A – Output Compare Register A Bit 7 6 5 4 (0xB3) 3 2 1 0 OCR2A[7:0] OCR2A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2).
ATmega164P/324P/644P • Bit 2 – OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2B is ready to be updated with a new value. • Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.
15.11.8 TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x17 (0x37) – – – – – OCF2B OCF2A TOV2 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR2 • Bit 2 – OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector.
ATmega164P/324P/644P 16. SPI – Serial Peripheral Interface 16.1 Features • • • • • • • • 16.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 16-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
ATmega164P/324P/644P When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 16-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 77. Table 16-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
ATmega164P/324P/644P The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
16.3 16.3.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega164P/324P/644P Table 16-2. SPI Modes SPI Mode Conditions Leading Edge Trailing Edge 0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) Figure 16-3.
16.5 16.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
ATmega164P/324P/644P • Bits 1:0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 16-5. 16.5.
16.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
ATmega164P/324P/644P 17. USART 17.1 Features • • • • • • • • • • • • 17.
Figure 17-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1. See Figure 1-1 on page 2 and “Alternate Port Functions” on page 77 for USART pin placement.
ATmega164P/324P/644P 17.4 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART Control and Status Register C (UCSRnC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA Register.
Table 17-1 on page 174 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each mode of operation using an internally generated clock source. Table 17-1.
ATmega164P/324P/644P 17.4.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 17-2 on page 173 for details. External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver.
17.5 Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • 5, 6, 7, 8, or 9 data bits • no, even or odd parity bit • 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit.
ATmega164P/324P/644P 17.5.1 Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted.
For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
ATmega164P/324P/644P 17.7.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame.
Assembly Code Example(1)(2) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRnB,TXB8 sbrc r17,0 sbi UCSRnB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDRn,r16 ret C Code Example(1)(2) void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
ATmega164P/324P/644P When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn.
The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used.
ATmega164P/324P/644P Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
17.8.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
ATmega164P/324P/644P 17.8.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits.
17.9.1 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 17-5 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation.
ATmega164P/324P/644P The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. Figure 17-7 on page 187 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 17-7.
Table 17-2 on page 188 and Table 17-3 on page 188 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. Table 17-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.
ATmega164P/324P/644P If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indicates if the frame contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame.
17.11 Register Description 17.11.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDRn Register location.
ATmega164P/324P/644P • Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit).UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable n Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag.
ATmega164P/324P/644P Table 17-4. Note: UMSELn Bits Settings UMSELn1 UMSELn0 Mode 0 1 Synchronous USART 1 0 (Reserved) 1 1 Master SPI (MSPIM)(1) 1. See “USART in SPI Mode” on page 199 for full description of the Master SPI Mode (MSPIM) operation • Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame.
Table 17-7. UCSZn Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 17-8.
ATmega164P/324P/644P 17.12 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 17-9 to Table 17-12. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
Table 17-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.
ATmega164P/324P/644P Table 17-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0.
Table 17-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz U2Xn = 0 Baud Rate (bps) UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 4800 207 0.2% 416 -0.1% 9600 103 0.2% 207 0.2% 14.4k 68 0.6% 138 -0.1% 19.2k 51 0.2% 103 0.2% 28.8k 34 -0.8% 68 0.6% 38.4k 25 0.2% 51 0.2% 57.6k 16 2.1% 34 -0.8% 76.8k 12 0.2% 25 0.2% 115.2k 8 -3.5% 16 2.1% 230.4k 3 8.5% 8 -3.5% 250k 3 0.0% 7 0.0% 0.5M 1 0.
ATmega164P/324P/644P 18. USART in SPI Mode 18.1 Features • • • • • • • • 18.
18.4 BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095) SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 18-1.
ATmega164P/324P/644P The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. 16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will then signal that the 16-bit value has been shifted out. 18.5.
Assembly Code Example(1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
ATmega164P/324P/644P 18.6 Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXENn bit in the UCSRnB register is set to one. When the Transmitter is enabled, the normal port operation of the TxDn pin is overridden and given the function as the Transmitter's serial output. Enabling the receiver is optional and is done by setting the RXENn bit in the UCSRnB register to one.
Assembly Code Example(1) USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRnA, UDREn rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDRn,r16 ; Wait for data to be received USART_MSPIM_Wait_RXCn: sbis UCSRnA, RXCn rjmp USART_MSPIM_Wait_RXCn ; Get and return received data from buffer in r16, UDRn ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
ATmega164P/324P/644P 18.7 AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: • Master mode timing diagram. • The UCPOLn bit functionality is identical to the SPI CPOL bit. • The UCPHAn bit functionality is identical to the SPI CPHA bit. • The UDORDn bit functionality is identical to the SPI DORD bit. However, since the USART in MSPIM mode reuses the USART resources, the use of the USART in MSPIM mode is somewhat different compared to the SPI.
18.8 Register Description The following section describes the registers used for SPI operation using the USART. 18.8.1 UDRn – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation. See “UDRn – USART I/O Data Register n” on page 190. 18.8.
ATmega164P/324P/644P 18.8.3 UCSRnB – USART MSPIM Control and Status Register n B Bit 7 6 5 4 3 2 1 RXCIEn TXCIEn UDRIE RXENn TXENn - - 0 - Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 1 1 0 UCSRnB • Bit 7 - RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn Flag.
18.8.4 UCSRnC – USART MSPIM Control and Status Register n C Bit 7 6 5 4 3 2 1 0 UMSELn1 UMSELn0 - - - UDORDn UCPHAn UCPOLn Read/Write R/W R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 UCSRnC • Bit 7:6 - UMSELn1:0: USART Mode Select These bits select the mode of operation of the USART as shown in Table 18-4. See “UCSRnC – USART Control and Status Register n C” on page 192 for full description of the normal USART operation.
ATmega164P/324P/644P 19. 2-wire Serial Interface 19.1 Features • • • • • • • • • • 19.
19.2.1 TWI Terminology The following definitions are frequently encountered in this section. Table 19-1. TWI Terminology Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus.
ATmega164P/324P/644P Figure 19-2. Data Validity SDA SCL Data Stable Data Stable Data Change 19.3.2 START and STOP Conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus.
The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK cycle. A general call is used when a Master wishes to transmit the same message to several slaves in the system.
ATmega164P/324P/644P 19.3.5 Combining Address and Data Packets into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by pulling the SCL line low.
Figure 19-7. SCL Synchronization Between Multiple Masters TA low TA high SCL from Master A SCL from Master B SCL Bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the Master had output, it has lost the arbitration.
ATmega164P/324P/644P Note that arbitration is not allowed between: • A REPEATED START condition and a data bit. • A STOP condition and a data bit. • A REPEATED START and a STOP condition. It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets.
19.5.1 SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section.
ATmega164P/324P/644P 19.5.4 Address Match Unit The Address Match unit checks if received address bytes match the seven-bit address in the TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the TWAR is written to one, all incoming address bits will also be compared against the General Call address. Upon an address match, the Control Unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.
Figure 19-10 is a simple example of how the application can interface to the TWI hardware. In this example, a Master wishes to transmit a single data byte to a Slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented. Application Action Figure 19-10. Interfacing the Application to the TWI in a Typical Transmission 1.
ATmega164P/324P/644P 5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR.
Assembly Code Example ldi 1 r16, (1<
ATmega164P/324P/644P 19.7 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
Figure 19-11. Data Transfer in Master Transmitter Mode VCC Device 1 Device 2 MASTER TRANSMITTER SLAVE RECEIVER Device 3 ........ R1 Device n R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag.
ATmega164P/324P/644P After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 19-2.
Figure 19-12.
ATmega164P/324P/644P Figure 19-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........ Device n R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 1 X 1 0 X 1 0 X TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 19-3.
ATmega164P/324P/644P Figure 19-14.
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
ATmega164P/324P/644P Table 19-4.
Figure 19-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
ATmega164P/324P/644P To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
Table 19-5.
ATmega164P/324P/644P Figure 19-18. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to slave From slave to master 19.7.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation.
ATmega164P/324P/644P • Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit.
19.9.2 TWCR – TWI Control Register Bit 7 6 5 4 3 2 1 0 TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Read/Write R/W R/W R/W R/W R R/W R R/W Initial Value 0 0 0 0 0 0 0 0 (0xBC) TWCR The TWCR is used to control the operation of the TWI.
ATmega164P/324P/644P • Bit 3 – TWWC: TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high. • Bit 2 – TWEN: TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters.
19.9.4 TWDR – TWI Data Register Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 (0xBB) TWDR In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware.
ATmega164P/324P/644P The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR. Figure 19-22 shows the address match logic in detail. Figure 19-22.
20. AC - Analog Comparator 20.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega164P/324P/644P Table 20-1. 20.3 20.3.1 Analog Comparator Mulitiplexed Input ACME ADEN MUX2..
• Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
ATmega164P/324P/644P 21. ADC - Analog-to-digital Converter 21.1 Features • • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 65 - 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution 8 Multiplexed Single Ended Input Channels Differential mode with selectable gain at 1x, 10x or 200x(1) Optional Left adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 2.7 - VCC Differential ADC Voltage Range Selectable 2.56V or 1.
Figure 21-1. Analog-to-digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] ADSC ADATE TRIGGER SELECT AREF ADC[9:0] ADIF ADPS[2:0] ADEN DIFF / GAIN SELECT CHANNEL SELECTION INTERNAL REFERENCE (1.1V/2.
ATmega164P/324P/644P If differential channels are selected, the differential gain stage amplifies the voltage difference between the selected input channel pair by the selected gain factor. This amplified value then becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set.
Figure 21-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
ATmega164P/324P/644P in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Differential Gain Channels” on page 249 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles.
Figure 21-5. ADC Timing Diagram, Single Conversion One Conversion Cycle Number 2 1 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample & Hold MUX and REFS Update Conversion Complete MUX and REFS Update Figure 21-6.
ATmega164P/324P/644P Table 21-1. ADC Conversion Time Condition Conversion Time (Cycles) First conversion 14.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.5 13/14 Auto Triggered conversions Normal conversions, differential 21.5.1 Sample & Hold (Cycles from Start of Conversion) Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to be taken into consideration.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: 1.
ATmega164P/324P/644P If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 21-8. Analog Input Circuitry IIH ADCn 1..
ATmega164P/324P/644P 21.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b.
21.7.4 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 21-10.
ATmega164P/324P/644P Figure 21-12. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 21-13.
21.8 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN ⋅ 1024 ADC = ---------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 21-3 on page 258 and Table 21-4 on page 259). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
ATmega164P/324P/644P Figure 21-14. Differential Measurement Range Output Code 0x1FF 0x000 - V REF/GAIN 0x3FF 0 VREF/GAIN Differential Input Voltage (Volts) 0x200 Table 21-2. Correlation between Input Voltage and Output Codes VADCn Read code Corresponding Decimal Value VADCm + VREF/GAIN 0x1FF 511 VADCm + 0.999 VREF/GAIN 0x1FF 511 VADCm + 0.998 VREF/GAIN 0x1FE 510 ... ... ... VADCm + 0.001 VREF/GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001 VREF/GAIN 0x3FF -1 ... ... ...
Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. 21.9 21.9.
ATmega164P/324P/644P Table 21-4. Input Channel and Gain Selections MUX4..
21.9.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega164P/324P/644P Table 21-5. 21.9.
• Bit 7, 5:3 – Res: Reserved Bits These bits are reserved for future use in the ATmega164P/324P/644P. For ensuring compability with future devices, these bits must be written zero when ADCSRB is written. • Bit 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.
ATmega164P/324P/644P 22. JTAG Interface and On-chip Debug System 22.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
22.3 TAP – Test Access Port The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are: • TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. • TCK: Test Clock. JTAG operation is synchronous to TCK. • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out.
ATmega164P/324P/644P Figure 22-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 22.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
ATmega164P/324P/644P A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 267. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work.
22.8 Using the JTAG Programming Capabilities Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the JTAG Test Access Port. The JTAG programming capability supports: • Flash programming and verifying.
ATmega164P/324P/644P 23. IEEE 1149.1 (JTAG) Boundary-scan 23.1 Features • • • • • 23.2 JTAG (IEEE std. 1149.
23.3 Data Registers The Data Registers relevant for Boundary-scan operations are: • Bypass Register • Device Identification Register • Reset Register • Boundary-scan Chain 23.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested.
ATmega164P/324P/644P Figure 23-2. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 23.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan Chain” on page 272 for a complete description. 23.
23.4.2 IDCODE; 0x1 Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input. 23.4.
ATmega164P/324P/644P The Boundary-scan logic is not included in the figures in the datasheet. Figure 23-4 shows a simple digital port pin as described in the section “I/O-Ports” on page 71. The Boundary-scan details from Figure 23-3 replaces the dashed box in Figure 23-4.
Figure 23-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR RESET OCxn WDx Q Pxn ODxn D PORTxn Q CLR WRx IDxn DATA BUS RDx RESET SLEEP RRx SYNCHRONIZER D Q D RPx Q PINxn L Q Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 23.5.
ATmega164P/324P/644P 23.6 ATmega164P/324P/644P Boundary-scan Order Table 23-1 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and Port K is scanned in the opposite bit order of the other ports.
Table 23-1. ATmega164P/324P/644P Boundary-scan Order (Continued) Bit Number Signal Name 39 PD0.Data 38 PD0.Control 37 PD1.Data 36 PD1.Control 35 PD2.Data 34 PD2.Control 33 PD3.Data 32 PD3.Control 31 PD4.Data 30 PD4.Control 29 PD5.Data 28 PD5.Control 27 PD6.Data 26 PD6.Control 25 PD7.Data 24 PD7.Control 23 PC0.Data 22 PC0.Control 21 PC1.Data 20 PC1.Control 19 PC2.Data 18 PC6.Data 17 PC6.Control 16 PC7.Data 15 PC7.
ATmega164P/324P/644P Table 23-1. 23.7 ATmega164P/324P/644P Boundary-scan Order (Continued) Bit Number Signal Name 14 PA7.Data 13 PA7.Control 12 PA6.Data 11 PA6.Control 10 PA5.Data 9 PA5.Control 8 PA4.Data 7 PA4.Control 6 PA3.Data 5 PA3.Control 4 PA2.Data 3 PA2.Control 2 PA1.Data 1 PA1.Control 0 PA0.
23.8 23.8.1 Register Description MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bits 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled.
ATmega164P/324P/644P 24. Boot Loader Support – Read-While-Write Self-Programming 24.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 24.2 1. A page is a section in the Flash consisting of several bytes (see Table 25-7 on page 299) used during programming.
24.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section.
ATmega164P/324P/644P Figure 24-1. Read-While-Write vs.
Figure 24-2.
ATmega164P/324P/644P Table 24-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
24.7 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file. Bit 23 22 21 20 19 18 17 15 14 13 12 11 10 9 16 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 25-7 on page 299), the Program Counter can be treated as having two different sections.
ATmega164P/324P/644P 24.8 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
24.8.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. • Page Write to the RWW section: The NRWW section can be read during the Page Write. • Page Write to the NRWW section: The CPU is halted during the operation. 24.8.
ATmega164P/324P/644P 24.8.8 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 24.8.
24.8.10 Reading the Signature Row from Software To read the Signature Row from software, load the Z-pointer with the signature byte address given in Table 24-5 on page 288 and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in SPMCSR, the signature byte value will be loaded in the destination register.
ATmega164P/324P/644P 24.8.12 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 24-6 on page 289 shows the typical programming time for Flash accesses from the CPU. Table 24-6. Symbol Min Programming Time Max Programming Time Flash write (Page Erase, Page Write, and write Lock bits by SPM) 3.7 ms 4.5 ms Note: 24.8.13 SPM Programming Time(1) 1. Minimum and maximum programming times is per individual operation.
ldi spmcrval, (1<
ATmega164P/324P/644P 24.8.14 ATmega164P Boot Loader Parameters In Table 24-7 through Table 24-9, the parameters used in the description of the Self-Programming are given. Table 24-7.
24.8.15 ATmega324P Boot Loader Parameters In Table 24-7 through Table 24-9, the parameters used in the description of the Self-Programming are given. Table 24-10.
ATmega164P/324P/644P 24.8.16 ATmega644P Boot Loader Parameters In Table 24-13 through Table 24-15, the parameters used in the description of the Self-Programming are given. Table 24-13.
24.9 24.9.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega164P/324P/644P • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
25. Memory Programming 25.1 Program And Data Memory Lock Bits The ATmega164P/324P/644P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 25-1.
ATmega164P/324P/644P Lock Bit Protection Modes(1)(2) (Continued) Table 25-2. Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
Table 25-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega164P/324P/644P 25.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 25.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
25.6 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega164P/324P/644P. Pulses are assumed to be at least 250 ns unless otherwise noted. 25.6.
ATmega164P/324P/644P Table 25-9. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O PAGEL PD7 I Program Memory and EEPROM data Page Load. BS2 PA0 I Byte Select 2. DATA PB7-0 I/O Function Bi-directional Data bus (Output when OE is low). Table 25-10.
Table 25-13. Command Byte Bit Encoding Command Byte 25.7 25.7.1 Command Executed 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3.
ATmega164P/324P/644P 25.7.4 Programming the Flash The Flash is organized in pages, see Table 25-7 on page 299. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4.
H. Load Address Extended High byte (Address bits 23..16) 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS2, BS1 to “10”. This selects the address extended high byte. 3. Set DATA = Address extended high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. I. Program Page 1. Set BS2, BS1 to “00” 2. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 3.
ATmega164P/324P/644P Figure 25-3. Programming the Flash Waveforms(1) F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G H ADDR. HIGH ADDR. EXT.H I XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL Note: 25.7.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 25-8 on page 299.
Figure 25-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 25.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 303 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. H: Load Address Extended Byte (0x00- 0xFF). 3. G: Load Address High Byte (0x00 - 0xFF). 4.
ATmega164P/324P/644P 25.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 303 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS2, BS1 to “01”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2, BS1 to “00”. This selects low data byte. 25.7.
25.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 303 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4. Set OE to “0”, and BS2, BS1 to “10”.
ATmega164P/324P/644P 25.7.15 Parallel Programming Characteristics Table 25-14. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min VPP Programming Enable Voltage 11.
Figure 25-7. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 25-8.
ATmega164P/324P/644P 25.8 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using a serial programming bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 25-15 on page 311, the pin mapping for serial programming is listed.
25.8.2 Serial Programming Algorithm When writing serial data to the ATmega164P/324P/644P, data is clocked on the rising edge of SCK. When reading data from the ATmega164P/324P/644P, data is clocked on the falling edge of SCK. See Figure 25-12 for timing details. To program and verify the ATmega164P/324P/644P in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 25-17): 1.
ATmega164P/324P/644P Table 25-16. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location 25.9 Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms Serial Programming Instruction set Table 25-17 on page 313 and Figure 25-11 on page 314 describes the Instruction set. Table 25-17.
Notes: 1. 2. 3. 4. 5. Not all instructions are applicable for all parts. a = address. Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. 7. See htt://www.atmel.
ATmega164P/324P/644P 25.9.1 Serial Programming Characteristics For characteristics of the Serial Programming module see “SPI Timing Characteristics” on page 333. Figure 25-12. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 25.10 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO.
Figure 25-13. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 25.10.2 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
ATmega164P/324P/644P 25.10.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
25.10.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section “Programming Specific JTAG Instructions” on page 315. The Data Registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register 25.10.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode.
ATmega164P/324P/644P Figure 25-15.
Table 25-18. JTAG Programming Instruction Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
ATmega164P/324P/644P Table 25-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d.
Table 25-18. JTAG Programming Instruction (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8e. Read Lock Bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8f.
ATmega164P/324P/644P Figure 25-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 1 1 0 1 Update-IR 0 1 0 25.10.
During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte Register during the Capture-DR state. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte.
ATmega164P/324P/644P 25.10.14 Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the programming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. 25.10.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3.
25.10.17 Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b, 3c and 3d. 4. Read data using programming instruction 3e. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3.
ATmega164P/324P/644P 25.10.20 Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data high byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. 4. Write Fuse High byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 25-14 on page 309). 6.
26. Electrical Characteristics Absolute Maximum Ratings* Operating Temperature................................. -55° C to +125° C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATmega164P/324P/644P 26.1 DC Characteristics TA = -40° C to 125° C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. VIL Input Low Voltage,Except XTAL1 and Reset pin VCC = 2.7V - 5.5V VIL1 Input Low Voltage, XTAL1 pin VIL2 Max. Units -0.5 0.3VCC(1) V VCC = 2.7V - 5.5V -0.5 0.1VCC(1) V Input Low Voltage, RESET pin VCC = 2.7V - 5.5V -0.5 0.3VCC(1) V VIH Input High Voltage, Except XTAL1 and RESET pins VCC = 2.7V - 5.5V 0.6VCC(2) VCC + 0.
4)The sum of all IOH, for ports F0-F7 should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Values indicated represent typical data from design simulation. 26.1.1 ATmega644P DC Characteristics Table 26-1. Symbol TA = -40° C to 125° C, VCC = 2.7V to 5.5V (unless otherwise noted) Parameter Condition Power Supply Current(1) ICC Power-down mode Min. Typ. Max.
ATmega164P/324P/644P 26.3 Clock Characteristics Table 26-2. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy 8.0 MHz 3V 25° C ±2% 2.7V - 5.5V -40° C - 125° C ±14% Factory Calibration 26.3.1 External Clock Drive Waveforms Figure 26-2. External Clock Drive Waveforms V IH1 V IL1 26.3.2 External Clock Drive Table 26-3. External Clock Drive(1) VCC=2.7-5.5V VCC=4.5-5.5V Symbol Parameter Min. Max. Min. Max.
26.4 System and Reset Characteristics Table 26-4. Symbol tRST (1) VHYST VRAM Reset, Brown-out and Internal Voltage Reference Characteristics Parameter Condition Min Minimum pulse width on RESET Pin Brown-out Detector Hysteresis (3) (1) tBOD RAM Retention Voltage (1) Min Pulse Width on Brown-out Reset VBG Bandgap reference voltage VC C= 2.7V, TA = 25° C tBG(1) Bandgap reference start-up time Bandgap reference current consumption IBG Notes: (1) Typ 1.0 Max Units 2.
ATmega164P/324P/644P 26.5 SPI Timing Characteristics See Figure 26-3 on page 333 and Figure 26-4 on page 334 for details. Table 26-6. SPI Timing Parameters(2) Description Mode 1 SCK period Master See Table 16-5 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master TBD 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 26-4. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 17 15 MISO (Data Output) 26.6 MSB ... LSB X 2-wire Serial Interface Characteristics Table 26-7 describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega164P/324P/644P 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 26-5. Table 26-7.
ATmega164P/324P/644P 2-wire Serial Bus Requirements(1) (Continued) Table 26-7. Symbol Parameter tHIGH High period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Notes: Condition Min Max Units fSCL ≤100 kHz 4.0 – µs fSCL > 100 kHz 0.6 – µs fSCL ≤100 kHz 4.7 – µs fSCL > 100 kHz 0.6 – µs fSCL ≤100 kHz 0 3.
26.7 ADC Characteristics Table 26-8. Symbol ADC Characteristics, Single Ended Channel INL DNL Max(1) Resolution Single Ended Conversion 10 Single Ended Conversion(1) VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2.5 4 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode 2.5 4 Integral Non-Linearity Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz 0.5 1.
ATmega164P/324P/644P Table 26-9. Symbol ADC Characteristics, Differential Channels Parameter Resolution TUE INL DNL Absolute Accuracy (Including INL, DNL Quantization Error and Offset Error) Integral Non-linearity Differential Non-linearity Gain Error Offset Error Condition Min(1) Typ(1) Gain = 1x 8 Gain = 10x 8 Gain = 200x 7 Max(1) Units Bits Gain = 1x, VCC =5 V, VREF = 4V ADC clock = 200 kHz(1)(3) 4.6 7 Gain = 10x, VCC =5 V, VREF = 4V ADC clock = 200 kHz(1)(3) 4.
27. ATmega644P Typical Characteristics • The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. • The power consumption in Power-down mode is independent of clock selection.
ATmega164P/324P/644P Figure 27-2. Active Supply Current vs. Frequency (1 - 20MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY Temp = 125°c 30 25 ICC (mA) 20 5.5 15 5 4.5 10 3.3 3 5 2.7 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 27-3. Active Supply Current vs. Vcc (Internal RC Oscillator 8 MHz) ACTIVE S UP P LY CURRENT vs . V CC INTERNAL RC OSCILLATOR, 8 MHz 12 125 85 25 -40 10 ICC (mA) 8 ˚C ˚C ˚C ˚C 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 27-4.
ACTIVE S UP P LY CURRENT vs . V CC INTERNAL RC OSCILLATOR, 1 MHz 3.5 3 125 85 25 -40 ICC (mA) 2.5 2 ˚C ˚C ˚C ˚C 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega164P/324P/644P Figure 27-5. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) - Temperature = 25°C IDLE S UP P LY CURRENT vs . LOW FREQUENCY NO POWER REDUCTION ENABLED - Te mpe ra ture = 25˚C 0.9 0.8 0.7 ICC (mA) 0.6 5.5 V 5.0 V 4.5 V 0.5 0.4 3.3 V 3.0 V 2.7 V 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Fre que nc y (MHz ) Figure 27-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) - Temperature = 125°C IDLE S UP P LY CURRENT vs . LOW FREQUENCY Te mpe ra ture = 125˚C 0.
Figure 27-7. Idle Supply Current vs. Frequency (1 - 20 MHz) - Temperature = 125°C IDLE SUPPLY CURRENT vs. FREQUENCY Temp = 125°c 10 9 ICC (mA) 8 7 5.5 6 5 5 4.5 4 3.3 3 3 2.7 2 1 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 27-8. Idle Supply Current vs. Vcc (Internal RC Oscillator 8 MHz) IDLE S UP P LY CURRENT vs . V CC INTERNAL RC OSCILLATOR, 8 MHz 3.5 3 ICC (mA) 2.5 125 85 25 -40 2 ˚C ˚C ˚C ˚C 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega164P/324P/644P Figure 27-9. Idle Supply Current vs. Vcc (Internal RC Oscillator 1 MHz) IDLE S UP P LY CURRENT vs . V CC INTERNAL RC OSCILLATOR, 1 MHz 0.8 0.7 0.6 125 85 25 -40 ICC (mA) 0.5 ˚C ˚C ˚C ˚C 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 27.1 Power-down Supply Current Figure 27-10. Power-down Supply Current vs. Vcc (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 25 20 15 ICC (uA) 125 85 25 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 27-11. Power-down Supply Current vs. Vcc (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 30 25 ICC (uA) 20 125 15 85 25 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 27.2 Power-save Supply Current Figure 27-12. Power-save Supply Current vs. Vcc (25°C, Watchdog Timer Disabled) P OWER-S AVE S UP P LY CURRENT vs . VC C WATCHDOG TIMER DISABLED 2 25 ˚C 1.8 1.6 ICC (uA) 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.
ATmega164P/324P/644P 27.3 Pin Pull-up Figure 27-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (Vcc = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5.0v 160 140 120 IOP (uA) 100 125 80 85 60 25 -45 40 20 0 0 1 2 3 4 5 6 V OP (V) Figure 27-14. Reset Pull-up Resistor Current vs. Reset Pin Voltage (Vcc = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5.0v 120 100 80 IRESET (uA) 125 60 85 25 40 -45 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
27.4 Pin Driver Strength Figure 27-15. I/O Pin Output Voltage vs. Source Current (Vcc = 5V) VOH VCC 5V, Load current up to 20 mA 5.1 125 85 5 25 4.9 -45 V OH (V) 4.8 4.7 4.6 4.5 4.4 4.3 0 2 4 6 8 10 12 14 16 18 20 Load current (mA) Figure 27-16. I/O Pin Output Voltage vs. Source Current (Vcc = 3.0V) VOH VCC 3V, Load current up to 20 mA 3.1 2.9 2.7 125 V OH (V) 2.5 85 2.3 25 2.1 -45 1.9 1.7 1.
ATmega164P/324P/644P Figure 27-17. I/O Pin Output Voltage vs. Sink Current (Vcc = 5V) VOL VCC 5V, Load current up to 20 mA 0.7 0.6 0.5 V OL (V) 125 0.4 85 25 0.3 -45 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 Load current (mA) Figure 27-18. I/O Pin Output Voltage vs. Sink Current (Vcc = 3.0V) VOL VCC 3V, Load current up to 20 mA 1.2 1 V OL (V) 0.8 125 85 0.6 25 -45 0.4 0.
27.5 Threshold and Hysteresis Figure 27-19. I/O Input Threshold Voltage vs. Vcc (VIH, I/O Pin Read as “1”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 3.5 3 Threshold (V) 2.5 2 125 1.5 85 25 1 -45 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 V CC (V) Figure 27-20. I/O Input Threshold Voltage vs. Vcc (VIL, I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 3.5 3 Threshold (V) 2.5 2 125 1.5 85 25 1 -45 0.5 0 1.5 2 2.5 3 3.5 4 4.
ATmega164P/324P/644P 27.6 BOD Thresholds and Analog Comparator Offset Figure 27-21. BOD Thresholds vs. Temperature (BOD level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BOD level = 4.3v 4.500 Threshold (V) 4.400 4.300 1 0 4.200 4.100 4.000 -50 -30 -10 10 30 50 70 90 110 130 150 Temperature (C) Figure 27-22. BOD Thresholds vs. Temperature (BOD level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BOD level = 2.7v 3.000 Threshold (V) 2.900 2.800 1 0 2.700 2.600 2.
Figure 27-23. Bandgap Voltage vs. Temperature BANDGAP VOLTAGE vs. TEMPERATURE 1.2 1.18 Bandgap Voltage (V) 1.16 1.14 1.12 1.1 1.08 5 1.06 3 1.04 1.02 1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (V) 27.7 Internal Oscillator Speed Figure 27-24. Watchdog Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 130 FRC (kHz) 125 6 120 5.5 5 115 4.5 3.3 110 3 2.
ATmega164P/324P/644P Figure 27-25. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.3 8.2 5.5 FRC (MHz) 8.1 5 4.5 8 3.3 3 7.9 2.7 7.8 7.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature Figure 27-26. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value - Vcc = 5V CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs.
27.8 Current Consumption of Peripheral Units Figure 27-27. Brownout Detector Current vs. Operating Voltage BROWNOUT DETECTOR CURRENT vs . VC C 30 125 85 25 -40 25 ICC (uA) 20 ˚C ˚C ˚C ˚C 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 27-28. ADC Current vs. Operating Voltage (ADC at 1 MHz) ADC CURRENT vs . VCC AREF = AVCC 350 300 125 ˚C 85 ˚C 25 ˚C ICC (uA) 250 -40 ˚C 200 150 100 50 0 2.5 3 3.5 4 4.5 5 5.
ATmega164P/324P/644P Figure 27-29. AREF External Reference Current vs. Operating Voltage AREF CURRENT vs . V C C WHEN US ED AS ADC REFERENCE 250 200 ICC (uA) 125 ˚C -40 ˚C 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) Figure 27-30. Analog Comparator Current vs. Operating Voltage ANALOG COMP ARATOR CURRENT vs . VC C 90 -40 25 85 125 80 70 ˚C ˚C ˚C ˚C ICC (uA) 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
Figure 27-31. Programming Current vs. Operating Voltage EEP ROM WRITE CURRENT vs . Vcc Ext Clk 20 18 16 ICC (mA) 14 12 -40 ˚C 10 25 ˚C 8 85 ˚C 125 ˚C 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 V CC (V) 27.9 Current Consumption in Reset and Reset Pulse Width Figure 27-32. Reset Supply Current vs. Operating Voltage (0.1 - 1.0 MHz) (Excluding Current Through the Reset Pull-up), Temperature = 25°C RES ET S UP P LY CURRENT vs . VC C EXCLUDING CURRENT THROUGH THE RESET PULLUP - Te mpe ra ture = 25˚C 0.18 5.
ATmega164P/324P/644P Figure 27-33. Reset Supply Current vs. Operating Voltage (1 - 20 MHz) (Excluding Current Through the Reset Pull-up), Temperature = 25°C RES ET S UP P LY CURRENT vs . VC C EXCLUDING CURRENT THROUGH THE RESET PULLUP - Te mpe ra ture = 25˚C 4 3.5 5.5 V 3 5.0 V ICC (mA) 2.5 4.5 V 2 3.3 V 3.0 V 2.7 V 1.5 1 0.5 0 0 2 4 6 8 10 12 14 16 18 20 Fre que nc y (MHz ) Figure 27-34. Minimum Reset Pulse Width vs. Operating Voltage MINIMUM RES ET P ULS E WIDTH vs .
28.
ATmega164P/324P/644P Address (0xC0) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page UCSR0A Name RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 190/206 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 238 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 -
Address Name (0x7E) DIDR0 (0x7D) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 262 - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 258 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 241 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (0x79) ADCH ADC Data Register High byte 260 261 (0x78) ADCL (0x77) Reserved - - - ADC Data Register Low byt
ATmega164P/324P/644P Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x1C (0x3C) Address EIFR Name - - - - - INTF2 INTF1 INTF0 Page 67 0x1B (0x3B) PCIFR - - - - PCIF3 PCIF2 PCIF1 PCIF0 68 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) TIFR2 - - - - - OCF2b OCF2A TOV2 160 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 138 0x15 (0x35) TIFR0 - - -
29.
ATmega164P/324P/644P Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ←PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ←PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ←PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ←1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ←0 None 2 LSL Rd Logical Shift Left Rd
Mnemonics Operands Description Operation Flags #Clocks PUSH Rr Push Register on Stack STACK ←Rr None 2 POP Rd Pop Register from Stack Rd ←STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
ATmega164P/324P/644P 30. Ordering Information 30.1 ATmega164P Speed (MHz)(3) 8-16 2.7 - 5.5V 8-16 Notes: Power Supply 2.7 - 5.5V Package(1) Operational Range (2) ML -40°C to +125°C (2) PW -40°C to +125°C Ordering Code ATmega164P-A15AZ ATmega164P-A15MZ 1. Green and Rohs packaging 2. Tape & Reel with Dry-pack delivery 3. For Speed vs. VCC see “Speed Grades” on page 330 Package Type ML 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) PW 44-pad, 7 x 7 x 1.
31. Packaging Information 31.
ATmega164P/324P/644P 31.
Notes: 1. Dimensioning and tolerancing conform to ASME Y14.5M. - 1994. 2. Dimensions b applies to metallized terminal and is measured between 0.15 and 0.30 mm from terminal TIP. If the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 3. Maximum package warpage is 0.05 mm. 4. Maximum allowable burrs is 0.076 mm in all directions. 5. Pin #1 ID on top will be laser marked. 6. This drawing conforms to JEDEC registered outline M0-220.
ATmega164P/324P/644P 32. Errata ATmega164P 32.1 ATmega164P Rev. B No known Errata. 32.2 ATmega164P Rev. A ADC differential mode not recommended above 85°C. 33. Errata ATmega324P 33.1 ATmega324P Rev. B No known Errata. 33.2 ATmega324P Rev. A ADC differential mode not recommended above 85°C. 34. Errata ATmega644P 34.1 ATmega644P Rev. B No known Errata. 34.2 ATmega644P Rev. A ADC differential mode not recommended above 85°.
35. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 35.1 Rev. 7674F-AVR-09/09 1. PW packaging information updated 35.2 Rev. 7674E-AVR-02/09 1. Note page 1 is removed: Differential Mode is not recommended above 85°C 2. Section 2.2.
ATmega164P/324P/644P 36. Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 3 2.1 Block Diagram ...................................................................................................3 2.
8 9 7.9 Timer/Counter Oscillator ..................................................................................38 7.10 Clock Output Buffer .........................................................................................38 7.11 System Clock Prescaler ..................................................................................38 7.12 Register Description ........................................................................................39 Power Management and Sleep Modes ....
ATmega164P/324P/644P 13 8-bit Timer/Counter0 with PWM ............................................................ 92 13.1 Features ..........................................................................................................92 13.2 Overview ..........................................................................................................92 13.3 Timer/Counter Clock Sources .........................................................................93 13.4 Counter Unit ..............
16 SPI – Serial Peripheral Interface ......................................................... 161 16.1 Features ........................................................................................................161 16.2 Overview ........................................................................................................161 16.3 SS Pin Functionality ......................................................................................166 16.4 Data Modes ..............................
ATmega164P/324P/644P 19.7 Transmission Modes .....................................................................................221 19.8 Multi-master Systems and Arbitration ............................................................234 19.9 Register Description ......................................................................................235 20 AC - Analog Comparator ..................................................................... 240 20.1 Overview ...................................
23.7 Boundary-scan Description Language Files ..................................................277 23.8 Register Description ......................................................................................278 24 Boot Loader Support – Read-While-Write Self-Programming ......... 279 24.1 Features ........................................................................................................279 24.2 Overview ................................................................................
ATmega164P/324P/644P 27.4 Pin Driver Strength ........................................................................................346 27.5 Threshold and Hysteresis ..............................................................................348 27.6 BOD Thresholds and Analog Comparator Offset ..........................................349 27.7 Internal Oscillator Speed ...............................................................................350 27.
ATmega164P/324P/644P 7674F–AVR–09/09
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