Datasheet

20
2513LS–AVR–03/2013
ATmega162/V
Changes from Rev.
2513D-04/03 to
Rev. 2513E-09/03
1. Removed “Preliminary” from the datasheet.
2. Added note on Figure 1 on page 2.
3. Renamed and updated “On-chip Debug System” to “JTAG Interface and On-chip
Debug System” on page 46.
4. Updated Table 18 on page 48 and Table 19 on page 50.
5. Updated “Test Access Port – TAP” on page 197 regarding JTAGEN.
6. Updated description for the JTD bit on page 207.
7. Added note on JTAGEN in Table 99 on page 233.
8. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Character-
istics” on page 264.
9. Added a proposal for solving problems regarding the JTAG instruction IDCODE in
“Errata” on page 18.
Changes from Rev.
2513C-09/02 to
Rev. 2513D-04/03
1. Updated the “Ordering Information” on page 14 and “Packaging Information” on page
15.
2. Updated “Features” on page 1.
3. Added characterization plots under “ATmega162 Typical Characteristics” on page
275.
4. Added Chip Erase as a first step under “Programming the Flash” on page 260 and
“Programming the EEPROM” on page 262.
5. Changed CAL7, the highest bit in the OSCCAL Register, to a reserved bit on page 39
and in “Register Summary” on page 8.
6. Changed CPCE to CLKPCE on page 41.
7. Corrected code examples on page 55.
8. Corrected OCn waveforms in Figure 52 on page 120.
9. Various minor Timer1 corrections.
10. Added note under “Filling the Temporary Buffer (Page Loading)” on page 224 about
writing to the EEPROM during an SPM Page Load.
11. Added section “EEPROM Write During Power-down Sleep Mode” on page 24.
12. Added information about PWM symmetry for Timer0 on page 98 and Timer2 on page
147.
13. Updated Table 18 on page 48, Table 20 on page 50, Table 36 on page 77, Table 83 on
page 205, Table 109 on page 247, Table 112 on page 267, and Table 113 on page 268.