Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VQFN 44 (7x7) 8-Bit 8 MHz I/O number 35

Features

• High-performance, Low-power AVR

8-bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 16K Bytes of In-System Self-programmable Flash program memory

– 512 Bytes EEPROM

– 1K Bytes Internal SRAM

– Write/Erase cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Up to 64K Bytes Optional External Memory Space

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two 16-bit Timer/Counters with Separate Prescalers, Compare Modes, and

Capture Modes

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– 35 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, and 44-pad MLF

• Operating Voltages

– 1.8 - 5.5V for ATmega162V

– 2.7 - 5.5V for ATmega162

• Speed Grades

– 0 - 8 MHz for ATmega162V (see Figure 113 on page 266)

– 0 - 16 MHz for ATmega162 (see Figure 114 on page 266)

8-bit

Microcontroller

with 16K Bytes

In-System

Programmable

Flash

ATmega162

ATmega162V

Summary

2513LS–AVR–03/2013

Summary of content (22 pages)

PAGE 1
Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 16K Bytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1K Bytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100,000 EEPR
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Pin Configurations Figure 1.
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ATmega162/V Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2.
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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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ATmega162/V • The timed sequence for changing the Watchdog Time-out period is disabled. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 56 for details. • The double buffering of the USART Receive Registers is disabled. See “AVR USART vs. AVR UART – Compatibility” on page 168 for details. • Pin change interrupts are not supported (Control Registers are located in Extended I/O). • One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible.
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Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
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ATmega162/V Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention 1. Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
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Register Summary 8 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) Reserved – – – – – – – – ..
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ATmega162/V Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x60) Reserved – – – – – – – – 0x3F (0x5F) SREG I T H S V N Z C 10 0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 13 SP6 SP5 SP4 SP3 SP2 SP1 UBRR1[11:8] SP0 0x3D (0x5D) (2) (2) 0x3C (0x5C) 0x3B (0x5B) Page SPL SP7 UBRR1H URSEL1 13 UCSR1C URSEL1 UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 189 GICR INT1 INT0 INT2 PCIE1 PCIE0 – IVSEL IVCE 61, 86 190
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Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x01 (0x21) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 187 0x00 (0x20) UBRR1L Notes: 10 USART1 Baud Rate Register Low Byte 190 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3.
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ATmega162/V Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd  Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd  Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl  Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd  Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd  Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two R
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Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC  PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC  PC + k + 1 None 1/2 None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd  Rr Rd+1:Rd  Rr+1:Rr LDI Rd, K Load Immediate Rd  K None 1 LD Rd, X Load Indirect Rd  (X) None 2 LD Rd, X+ Load Indirect and Post-Inc.
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ATmega162/V Mnemonics Operands CLH Description Operation Clear Half Carry Flag in SREG H0 Flags #Clocks H 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr.
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Ordering Information Speed (MHz) 8(3) (4) 16 Notes: Package(1) Operation Range 1.8 - 5.5V ATmega162V-8AU ATmega162V-8PU ATmega162V-8MU 44A 40P6 44M1 Industrial (-40C to 85C) 2.7 - 5.5V ATmega162-16AU ATmega162-16PU ATmega162-16MU 44A 40P6 44M1 Industrial (-40C to 85C) Power Supply Ordering Code(2) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
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ATmega162/V Packaging Information 44A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
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40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion.
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ATmega162/V 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig.
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Errata The revision letter in this section refers to the revision of the ATmega162 device. ATmega162, all rev. There are no errata for this revision of ATmega162. However, a proposal for solving problems regarding the JTAG instruction IDCODE is presented below. • IDCODE masks data from TDI input • Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request • Interrupts may be lost when writing the timer register in asynchronous timer 1.
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ATmega162/V Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 1. Updated “Ordering Information” on page 14: Removed -AI, -PI and -MI ordering codes. Only Pb-free package options are available. 2513K-08/07 to Rev. 2513L-03/13 Changes from Rev. 1. Updated “Errata” on page 18. 2513J-08/07 to 2. Updated the last page with Atmel’s new addresses.
PAGE 20
Changes from Rev. 1. Removed “Preliminary” from the datasheet. 2513D-04/03 to 2. Added note on Figure 1 on page 2. Rev. 2513E-09/03 3. Renamed and updated “On-chip Debug System” to “JTAG Interface and On-chip Debug System” on page 46. 4. Updated Table 18 on page 48 and Table 19 on page 50. 5. Updated “Test Access Port – TAP” on page 197 regarding JTAGEN. 6. Updated description for the JTD bit on page 207. 7. Added note on JTAGEN in Table 99 on page 233. 8.
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ATmega162/V 14. Added Figures for “Absolute Maximum Frequency as a function of VCC, ATmega162” on page 266. 15. Updated Figure 29 on page 64, Figure 32 on page 68, and Figure 88 on page 210. 16. Removed Table 114, “External RC Oscillator, Typical Frequencies(1),” on page 265. 17. Updated “Electrical Characteristics” on page 264. Changes from Rev. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. 2513B-09/02 to Rev. 2513C-09/02 Changes from Rev. 1. Added information for ATmega162U.
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