Datasheet

79
ATmega162/V
2513G–AVR–03/05
• RXD0 – Port D, Bit 0
RXD0, Receive Data (Data input pin for USART0). When the USART0 Receiver is
enabled this pin is configured as an input regardless of the value of DDD0. When
USART0 forces this pin to be an input, the pull-up can still be controlled by the PORTD0
bit.
Table 39 and Table 40 relate the alternate functions of Port D to the overriding signals
shown in Figure 32 on page 67.
Table 39. Overriding Signals for Alternate Functions PD7..PD4
Signal Name PD7/RD PD6/WR PD5/TOSC2/OC1A PD4/TOSC1/XCK0/OC3A
PUOE SRE SRE AS2 AS2
PUOV 0 0 0 0
DDOE SRE SRE AS2 AS2
DDOV 1 1 0 0
PVOE SRE SRE OC1A ENABLE XCK0 OUTPUT ENABLE |
OC3A ENABLE
PVOV RD
WR OC1A if (XCK0 OUTPUT
ENABLE) then
XCK0 OUTPUT
else
OC3A
DIEOE 0 0 AS2 AS2
DIEOV 0 0 0 0
DI – – – XCK0 INPUT
AIO – – T/C2 OSC OUTPUT T/C2 OSC INPUT
Table 40. Overriding Signals for Alternate Functions in PD3..PD0
Signal Name PD3/INT1 PD2/INT0/XCK1 PD1/TXD0 PD0/RXD0
PUOE 0 0 TXEN0 RXEN0
PUOV 0 0 0 PORTD0 • PUD
DDOE 0 0 TXEN0 RXEN0
DDOV 0 0 1 0
PVOE 0 XCK1 OUTPUT ENABLE TXEN0 0
PVOV 0 XCK1 TXD0 0
DIEOE INT1 ENABLE INT0 ENABLE 0 0
DIEOV 1 1 0 0
DI INT1 INPUT/
ICP1 INPUT
INT0 INPUT/XCK1 INPUT – RXD0
AIO – – – –