Datasheet

50
ATmega162/V
2513G–AVR–03/05
Figure 25. Brown-out Reset During Operation
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
t
TOUT
. Refer to page 51 for details on operation of the Watchdog Timer.
Figure 26. Watchdog Reset During Operation
MCU Control and Status
Register – MCUCSR
The MCU Control and Status Register provides information on which reset source
caused an MCU Reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or
by writing a logic zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
V
CC
RESET
TIME-OUT
I
NTERNAL
RESET
V
BOT-
V
BOT+
t
TOUT
CK
CC
Bit 76543210
JTD – SM2 JTRF WDRF BORF EXTRF PORF MCUCSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description