Datasheet

47
ATmega162/V
2513G–AVR–03/05
Figure 21. Reset Logic
Note: 1. The Power-on Reset will not work unless the supply voltage has been below V
POT
(falling)
Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-
tion level is defined in Table 18. The POR is activated whenever V
CC
is below the
detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to
detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is Reset from Power-on.
Reaching the Power-on Reset threshold voltage invokes the delay counter, which deter-
mines how long the device is kept in RESET after V
CC
rise. The RESET signal is
activated again, without any delay, when V
CC
decreases below the detection level.
Table 18. Reset Characteristics
Symbol Parameter Condition Min. Typ. Max. Units
V
POT
Power-on Reset
Threshold Voltage (rising)
T
A
= -40 - 85°C0.7 1.0 1.4 V
Power-on Reset
Threshold Voltage
(falling)
(1)
T
A
= -40 - 85°C0.6 0.9 1.3 V
V
RST
RESET Pin Threshold
Voltage
V
CC
= 3V 0.1 V
CC
0.9 V
CC
V
t
RST
Minimum pulse width on
RESET Pin
V
CC
= 3V 2.5 µs
MCU Control and Status
Register (MCUCSR)
BODLEVEL [ 2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA B U S
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
JTRF
JTAG Reset
Register
Watchdog
Oscillator
SUT[1:0]
Watchdog
Timer
V
CC
RESET
Reset Circuit
Brown-out
Reset Circuit
Power-on
Reset Circuit
COUNTER RESET
INTERNAL RESET