Datasheet

214
ATmega162/V
2513G–AVR–03/05
51 PD7.Pullup_Enable Port D
50 EXTCLKEN Enable signals for main
Clock/Oscillators
49 OSCON
48 OSC32EN
47 EXTCLK (XTAL1) Clock input and Oscillators
for the main clock (Observe-
only)
46 OSCCK
45 OSC32CK
44 PC0.Data Port C
43 PC0.Control
42 PC0.Pullup_Enable
41 PC1.Data
40 PC1.Control
39 PC1.Pullup_Enable
38 PC2.Data
37 PC2.Control
36 PC2.Pullup_Enable
35 PC3.Data
34 PC3.Control
33 PC3.Pullup_Enable
32 PE2.Data Port E
31 PE2.Control
30 PE2.Pullup_Enable
29 PE1.Data
28 PE1.Control
27 PE1.Pullup_Enable
26 PE0.Data
25 PE0.Control
24 PE0.Pullup_Enable
23 PA7.Data Port A
22 PA7.Control
21 PA7.Pullup_Enable
20 PA6.Data
19 PA6.Control
18 PA6.Pullup_Enable
17 PA5.Data
16 PA5.Control
Table 88. ATmega162 Boundary-scan Order (Continued)
Bit Number Signal Name Module