Datasheet

189
ATmega162/V
2513G–AVR–03/05
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits
(Character Size) in a frame the receiver and transmitter use.
• Bit 0 – UCPOL: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous
mode is used. The UCPOL bit sets the relationship between data output change and
data input sample, and the synchronous clock (XCK).
USART Baud Rate Registers –
UBRRL and UBRRH
(1)
Note: 1. The UBRRH Register shares the same I/O location as the UCSRC Register. See the
“Accessing UBRRH/ UCSRC Registers” on page 183 section which describes how to
access this register.
• Bit 15 – URSEL: Register Select
This bit selects between accessing the UBRRH or the UCSRC Register. It is read as
zero when reading UBRRH. The URSEL must be zero when writing the UBRRH.
• Bit 14:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit
must be written to zero when UBRRH is written.
Table 76. UCSZ Bits Settings
UCSZ2 UCSZ1 UCSZ0 Character Size
0005-bit
0016-bit
0107-bit
0118-bit
100Reserved
101Reserved
110Reserved
1119-bit
Table 77. UCPOL Bit Settings
UCPOL
Transmitted Data Changed
(Output of TxD Pin)
Received Data Sampled
(Input on RxD Pin)
0 Rising XCK Edge Falling XCK Edge
1 Falling XCK Edge Rising XCK Edge
Bit 151413121110 9 8
URSEL – – – UBRR[11:8] UBRRH
UBRR[7:0] UBRRL
76543210
Read/Write R/W R R R R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000