Datasheet

ATmega162/V

2513G–AVR–03/05

Timer/Counter1 Control

Timer/Counter3 Control

• Bit 7 – ICNCn: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture noise canceler. When the noise can-

celer is activated, the input from the Input Capture pin (ICPn) is filtered. The filter

function requires four successive equal valued samples of the ICPn pin for changing its

output. The Input Capture is therefore delayed by four Oscillator cycles when the noise

canceler is enabled.

• Bit 6 – ICESn: Input Capture Edge Select

This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a cap-

ture event. When the ICESn bit is written to zero, a falling (negative) edge is used as

trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the

capture.

When a capture is triggered according to the ICESn setting, the counter value is copied

into the Input Capture Register (ICRn). The event will also set the Input Capture Flag

(ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is

enabled.

When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in

the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently

the Input Capture function is disabled.

• Bit 5 – Reserved Bit

This bit is reserved for future use. For ensuring compatibility with future devices, this bit

must be written to zero when TCCRnB is written.

• Bit 4:3 – WGMn3:2: Waveform Generation Mode

See TCCRnA Register description.

Bit 76543210

ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0