Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Non-volatile Program and Data Memories – 16K Bytes of In-System Self-programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programm
Pin Configurations Figure 1.
ATmega162/V Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega162/V ATmega161 Compatibility Mode Programming the M161C will change the following functionality: • The extended I/O map will be configured as internal RAM once the M161C Fuse is programmed. • The timed sequence for changing the Watchdog Time-out period is disabled. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 55 for details. • The double buffering of the USART Receive Registers is disabled. See “AVR USART vs.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega162/V AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register.
ATmega162/V The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers.
General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega162/V The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5.
Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
ATmega162/V also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-programming” on page 216. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
ATmega162/V AVR ATmega162 Memories This section describes the different memories in the ATmega162. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega162 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATmega162 contains 16K bytes On-chip In-System Reprogrammable Flash memory for program storage.
SRAM Data Memory Figure 9 shows how the ATmega162 SRAM Memory is organized. Memory configuration B refers to the ATmega161 compatibility mode, configuration A to the noncompatible mode. The ATmega162 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega162/V When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 (+160) I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega162 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10. Figure 9.
EEPROM Data Memory The ATmega162 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
ATmega162/V The EEPROM Data Register – EEDR Bit 7 6 5 4 3 2 1 MSB 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EEDR • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.
can be omitted. See “Boot Loader Support – Read-While-Write Self-programming” on page 216 for details about boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail.
ATmega162/V The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega162/V Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC Reset Protection circuit can be used. If a Reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
External Memory Interface With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as external SRAM and FLASH, and peripherals such as LCD-display, A/D, and D/A.
ATmega162/V The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and the Special Function IO Register – SFIOR. When the XMEM interface is enabled, it will override the settings in the Data Direction registers corresponding to the ports dedicated to the interface. For details about this port override, see the alternate functions in section “I/O-Ports” on page 62.
Pull-up and Bus Keeper The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep. The XMEM interface also provides a bus keeper on the AD7:0 lines. The Bus Keeper can be disabled and enabled in software as described in “Special Function IO Register – SFIOR” on page 30.
ATmega162/V Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) ALE Prev. addr. DA7:0 Prev. data Address Address XX Write A15:8 Data WR DA7:0 (XMBK = 1) Address Prev. data Data Address Read DA7:0 (XMBK = 0) Data RD Note: 1.
Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1) T1 T2 T3 T4 T5 T6 T7 System Clock (CLKCPU ) ALE Prev. addr. DA7:0 Prev. data Address Address XX Write A15:8 Data WR DA7:0 (XMBK = 1) Address Prev. data Data Address Read DA7:0 (XMBK = 0) Data RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector).
ATmega162/V SRAM address space is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits. Table 2. Sector Limits with Different Settings of SRL2..
Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 6 – XMBK: External Memory Bus Keeper Enable Writing XMBK to one enables the Bus Keeper on the AD7:0 lines. When the Bus Keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-stated the lines. Writing XMBK to zero disables the Bus Keeper.
ATmega162/V When the device is set in ATmega161 compatibility mode, the internal address space is 1,120 bytes. This implies that the first 1,120 bytes of the external memory can be accessed at addresses 0x8000 to 0x845F. To the Application software, the external 32 KB memory will appear as one linear 32 KB address space from 0x0460 to 0x845F. Figure 17.
Using all 64KB Locations of External Memory Since the external memory is mapped after the internal memory as shown in Figure 11, only 64,256 Bytes of external memory are available by default (address space 0x0000 to 0x05FF is reserved for internal memory). However, it is possible to take advantage of the entire external memory by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address.
ATmega162/V System Clock and Clock Options Clock Systems and their Distribution Figure 18 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 41. The clock systems are detailed below. Figure 18.
Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 5. Device Clocking Options Select Device Clocking Option CKSEL3..
ATmega162/V Figure 19. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3:1 as shown in Table 7. Table 7. Crystal Oscillator Operating Modes CKSEL3:1 Frequency Range (MHz) Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) 100(1) 0.4 - 0.9 – 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 12 - 22 Note: 1.
Notes: Low-frequency Crystal Oscillator 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up.
ATmega162/V Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 233. Table 11. Internal Calibrated RC Oscillator Operating Modes CKSEL3:0 Nominal Frequency (1) 0010 Note: 8.0 MHz 1. The device is shipped with this option selected. When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 12. XTAL1 and XTAL2 should be left unconnected (NC). Table 12.
Table 13. Internal RC Oscillator Frequency Range. External Clock OSCCAL Value Min Frequency in Percentage of Nominal Frequency Max Frequency in Percentage of Nominal Frequency 0x00 50% 100% 0x3F 75% 150% 0x7F 100% 200% To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 20. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 20.
ATmega162/V will be output also during Reset and the normal operation of PortB will be overridden when the fuse is programmed. Any clock sources, including Internal RC Oscillator, can be selected when PortB 0 serves as clock output. If the system clock prescaler is used, it is the divided system clock that is output when the CKOUT Fuse is programmed. See “System Clock Prescaler” on page 39. for a description of the system clock prescaler.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting.
ATmega162/V Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
Extended MCU Control Register – EMCUCR Bit 7 6 5 4 3 2 1 0 SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EMCUCR • Bit 7 – SM0: Sleep Mode Select Bit 0 The Sleep Mode Select bits select between the five available sleep modes as shown in Table 16. Table 16.
ATmega162/V Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-save mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep.
Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
ATmega162/V the logic level, power consumption will increase. Note that the TDI pin for the next device in the scan chain contains a pull-up that avoids this problem. Writing the JTD bit in the MCUCSR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface.
System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega162/V Figure 21. Reset Logic DATA BUS Power-on Reset Circuit BODLEVEL [ 2..0] Brown-out Reset Circuit INTERNAL RESET VCC PORF BORF EXTRF WDRF JTRF MCU Control and Status Register (MCUCSR) RESET SPIKE FILTER Reset Circuit JTAG Reset Register Watchdog Timer COUNTER RESET Pull-up Resistor Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 18. Reset Characteristics Symbol VPOT Condition Min. Typ. Max.
Figure 22. MCU Start-up, RESET Tied to VCC. VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 23. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 18) will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset.
ATmega162/V Brown-out Detection ATmega162 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. Table 19. BODLEVEL Fuse Coding BODLEVEL Fuses [2:0] Min.
Figure 25. Brown-out Reset During Operation VCC VBOT+ VBOT- RESET tTOUT TIME-OUT INTERNAL RESET Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 51 for details on operation of the Watchdog Timer. Figure 26.
ATmega162/V • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
shown in Table 22. Safety level 0 corresponds to the setting in ATmega161. There is no restriction on enabling the WDT in any of the safety levels. Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 55 for details. Table 22. WDT Configuration as a Function of the Fuse Settings of M161C and WDTON.
ATmega162/V if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above.
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega162/V Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the three safety levels. Separate procedures are described for each level. Safety Level 0 This mode is compatible with the Watchdog operation found in ATmega161. The Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction. The Time-out period can be changed at any time without restriction.
Interrupts Interrupt Vectors in ATmega162 This section describes the specifics of the interrupt handling as performed in ATmega162. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 24 shows the interrupt table when the compatibility fuse (M161C) is unprogrammed, while Table 25 shows the interrupt table when M161C Fuse is programmed.
ATmega162/V Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-programming” on page 216. 2. When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of the Boot Flash section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash section. Table 25. Reset and Interrupt Vectors if M161C is programmed Vector No.
Table 26 shows Reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 26.
ATmega162/V 0x03A ldi r16,low(RAMEND) 0x03B out SPL,r16 0x03C sei 0x03D ... ; Enable interrupts ... xxx ...
When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .
ATmega162/V IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega162/V Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 29 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 29.
enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the SFIOR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.
ATmega162/V Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATmega162/V Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
Table 28 summarizes the function of the overriding signals. The pin and port indexes from Figure 32 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 28. Generic Description of Overriding Signals for Alternate Functions. Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATmega162/V Special Function IO Register – SFIOR Bit 7 6 5 4 3 2 1 0 TSM XMBK XMM2 XMM1 XMM0 PUD PSR2 PSR310 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 2 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 63 for more details about this feature.
Table 30. Overriding Signals for Alternate Functions in PA7..
ATmega162/V Alternate Functions Of Port B The Port B pins with alternate functions are shown in Table 32. Table 32.
OC3B, Output Compare Match B output: The PB4 pin can serve as an external output for the Timer/Counter3 Output Compare B. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function. • AIN1/TXD1 – Port B, Bit 3 AIN1, Analog Comparator Negative input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
ATmega162/V Table 33. Overriding Signals for Alternate Functions in PB7..
Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 35. If the JTAG interface is enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be activated even if a reset occurs. Table 35.
ATmega162/V • A13/TMS/PCINT13 – Port C, Bit 5 A13, External memory interface address bit 13. TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. PCINT13: The pin can also serve as a pin change interrupt. • A12/TCK/PCINT12 – Port C, Bit 4 A12, External memory interface address bit 12. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK.
Table 36. Overriding Signals for Alternate Functions in PC7..
ATmega162/V Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 38. Table 38.
• TOSC1/XCK0/OC3A – Port D, Bit 4 TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PD4 is disconnected from the port, and becomes the input of the inverting Oscillator Amplifier. In this mode, a crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. XCK0, USART0 External Clock: The Data Direction Register (DDD4) controls whether the clock is output (DDD4 set (one)) or input (DDD4 cleared (zero)).
ATmega162/V • RXD0 – Port D, Bit 0 RXD0, Receive Data (Data input pin for USART0). When the USART0 Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When USART0 forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit. Table 39 and Table 40 relate the alternate functions of Port D to the overriding signals shown in Figure 32 on page 67. Table 39. Overriding Signals for Alternate Functions PD7..
Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 41. Table 41.
ATmega162/V Register Description for I/O-Ports Port A Data Register – PORTA Bit Port A Data Direction Register – DDRA Port A Input Pins Address – PINA 7 6 5 4 3 2 1 0 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6
Port C Input Pins Address – PINC Bit 7 6 5 4 3 2 1 0 PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 Read/Write R R R R R R R R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PINC Port D Data Register – PORTD Bit Port D Data Direction Register – DDRD Port D Input Pins Address – PIND 7 6 5 4 3 2 1 0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6
ATmega162/V External Interrupts The External Interrupts are triggered by the INT0, INT1, INT2 pin, or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2..0 or PCINT15..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt).
Table 43. Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request. 0 1 Any logical change on INT1 generates an interrupt request. 1 0 The falling edge of INT1 generates an interrupt request. 1 1 The rising edge of INT1 generates an interrupt request.
ATmega162/V General Interrupt Control Register – GICR Bit 7 6 5 4 3 2 1 0 INT1 INT0 INT2 PCIE1 PCIE0 – IVSEL IVCE Read/Write R/W R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GICR • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
General Interrupt Flag Register – GIFR Bit 7 6 5 4 3 2 1 INTF1 INTF0 INTF2 PCIF1 PCIF0 – – 0 – Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 GIFR • Bit 7 – INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
ATmega162/V Pin Change Mask Register 1 – PCMSK1 Bit 7 6 5 4 3 2 1 0 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT9 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK1 • Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8 Each PCINT15..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15..
8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 33.
ATmega162/V inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0). See “Output Compare Unit” on page 90. for details.
Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 34 shows a block diagram of the counter and its surroundings. Figure 34. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count TCNTn clear Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement.
ATmega162/V Figure 35 shows a block diagram of the output compare unit. Figure 35. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int.Req.) top bottom Waveform Generator OCn FOCn WGMn1:0 COMn1:0 The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the output compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0 value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting.
ATmega162/V The design of the output compare pin logic allows initialization of the OC0 state before the output is enabled. Note that some COM01:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 99. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM01:0 bits differently in Normal, CTC, and PWM modes.
Figure 37. CTC Mode, Timing Diagram OCn Interrupt Flag Set TCNTn OCn (Toggle) Period (COMn1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega162/V non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0. Figure 38. Fast PWM Mode, Timing Diagram OCRn Interrupt Flag Set OCRn Update ans TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX.
Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while up-counting, and set on the Compare Match while down-counting.
ATmega162/V between OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = ----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Figure 41. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 42 shows the setting of OCF0 in all modes except CTC mode. Figure 42. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 43 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 43.
ATmega162/V 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode.
When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 48 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a Normal or CTC mode (non-PWM). Table 48. Compare Output Mode, non-PWM Mode COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected. 0 1 Toggle OC0 on Compare Match. 1 0 Clear OC0 on Compare Match. 1 1 Set OC0 on Compare Match.
ATmega162/V • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 51. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge.
• Bit 0 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable When the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
ATmega162/V Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to Timer/Counter3, Timer/Counter1, and Timer/Counter0. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
ATmega162/V 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e.
Figure 46. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATABUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: Registers TCCRnB 1.
ATmega162/V (OCnA/B). See “Output Compare Units” on page 114. The Compare Match event will also set the Compare Match Flag (OCFnA/B) which can be used to generate an output compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See “Analog Comparator” on page 194.
Accessing 16-bit Registers The TCNTn, OCRnA/B, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same Temporary Register is shared between all 16bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
ATmega162/V Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B or ICRn Registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B or ICRn Registers can be done by using the same principle.
ATmega162/V Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter Control Register B (TCCRnB). For details on c l oc k s ou r c e s a n d p re s c al er , s e e “Ti m e r/ C o u nt e r0 , Ti me r /C ou n te r 1, a n d Timer/Counter3 Prescalers” on page 103.
how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 117. The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
ATmega162/V Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value.
(ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle.
ATmega162/V sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx directly.
Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The waveform generator uses the COMnx1:0 bits for defining the output compare (OCnx) state at the next Compare Match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 50 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega162/V Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next Compare Match. For Compare Output actions in the non-PWM modes refer to Table 53 on page 127.
Figure 51. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega162/V Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5,6,7,14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is set on the Compare Match between TCNTn and OCRnx, and cleared at TOP.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a Compare Match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value.
ATmega162/V Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM.
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value.
ATmega162/V Compare Match while down-counting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dualslope PWM modes, these modes are preferred for motor control applications.
When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers. If the TOP value is lower than any of the compare registers, a Compare Match will never occur between the TCNTn and the OCRnx. As Figure 54 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal.
ATmega162/V Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 55 shows a timing diagram for the setting of OCFnx. Figure 55.
Figure 57. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) Old OCRnx Value New OCRnx Value Figure 58 shows the same timing data, but with the prescaler enabled. Figure 58.
ATmega162/V 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter3 Control Register A – TCCR3A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 COM3A1 COM3A0 COM3B1 COM3B0 FOC3A FOC3B WGM31 WGM30 Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A TCCR3A •
Table 54 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 54. Compare Output Mode, Fast PWM(1) COMnA1/ COMnB1 COMnA0/ COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 15: Toggle OCnA on Compare Match, OCnB disconnected (normal port operation). For all other WGMn settings, normal port operation, OCnA/OCnB disconnected. 1 0 Clear OCnA/OCnB on Compare Match, set OCnA/OCnB at TOP.
ATmega162/V • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 56. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 117.) Table 56.
Timer/Counter1 Control Register B – TCCR1B Timer/Counter3 Control Register B – TCCR3B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B TCCR3B • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) ac
ATmega162/V • Bit 2:0 – CSn2:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 55 and Figure 56. Table 57. Clock Select Bit Description Timer/Counter1 CS12 CS11 CS10 Description 0 0 0 No clock source. (Timer/Counter stopped).
Timer/Counter1 – TCNT1H and TCNT1L Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] Timer/Counter3 – TCNT3H and TCNT3L TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCNT3[15:8] TCNT3H TCNT3[7:0] TCNT3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for writ
ATmega162/V The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OCnx pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP).
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 56.) is executed when the OCF1B Flag, located in TIFR, is set.
ATmega162/V Timer/Counter Interrupt Flag Register – TIFR(1) Bit 7 6 5 4 3 2 1 0 TOV1 OCF1A OC1FB OCF2 ICF1 TOV2 TOV0 OCF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: TIFR 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective Timer sections.
Extended Timer/Counter Interrupt Flag Register – ETIFR(1) Bit 7 6 5 4 3 2 1 ICF3 OCF3A OC3FB TOV3 – 0 – Read/Write R R R/W R/W R/W R/W R R Initial Value 0 0 0 0 0 0 0 0 Note: ETIFR 1. This register contains flag bits for several Timer/Counters, but only Timer3 bits are described in this section. The remaining bits are described in their respective Timer sections.
ATmega162/V 8-bit Timer/Counter2 with PWM and Asynchronous operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the Timer Clock (clkT2).
ATmega162/V Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 60 shows a block diagram of the counter and its surrounding environment. Figure 60. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement.
Figure 61. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int.Req.) top bottom Waveform Generator OCxy FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence.
ATmega162/V resulting in incorrect Waveform Generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is down-counting. The Setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between Waveform Generation modes.
The design of the Output Compare pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 148. Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in Normal, CTC, and PWM modes.
ATmega162/V Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events.
Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 1) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM.
ATmega162/V The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnPWM = ----------------N ⋅ 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle.
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to three (See Table 63 on page 150).
ATmega162/V Figure 66. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 67 shows the same timing data, but with the prescaler enabled. Figure 67. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 68 shows the setting of OCF2 in all modes except CTC mode. Figure 68.
Figure 69.
ATmega162/V match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 60 and “Modes of Operation” on page 142. Table 60. Waveform Generation Mode Bit Description(1) Mode WGM21 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation TOP Update of OCR2 at TOV2 Flag Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM 0xFF TOP MAX Note: 1.
• Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting.
ATmega162/V • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 64. Table 64. Clock Select Bit Description Timer/Counter Register – TCNT2 Description CS22 CS21 CS20 0 0 0 No clock source (Timer/Counter stopped).
Asynchronous operation of the Timer/Counter Asynchronous Status Register – ASSR Bit 7 6 5 4 3 2 1 0 – – – – AS2 TCN2UB OCR2UB TCR2UB Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin.
ATmega162/V Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2, and TCCR2. 4.
down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or Extended Standby mode when the Timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the Timer is always advanced by at least one before the processor can read the counter value.
ATmega162/V Timer/Counter Interrupt Flag Register – TIFR Bit 7 6 5 4 3 2 1 0 TOV1 OCF1A OC1FB OCF2 ICF1 TOV2 TOV0 OCF0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 4 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector.
Figure 70. Prescaler for Timer/Counter2 clkT2S PSR2 clkT2S/1024 clkT2S/256 clkT2S/8 AS2 clkT2S/128 10-BIT T/C PRESCALER Clear TOSC1 clkT2S/64 clkI/O clkT2S/32 Timer/Counter Prescaler 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
ATmega162/V Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega162 and peripheral devices or between several AVR devices.
When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the End of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested.
ATmega162/V The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO, and DD_SCK must be replaced by the actual data direction bits for these pins. E.g., if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
The following code examples show how to initialize the SPI as a slave and how to perform a simple reception.
ATmega162/V SS Pin Functionality Slave Mode When the SPI is configured as a slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
• Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 73 and Figure 74 for an example.
ATmega162/V SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF Flag.
Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 73 and Figure 74. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 66 and Table 67, as done below: Table 69.
ATmega162/V USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
Figure 75. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATABUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1. Refer to Figure 1 on page 2, Table 34 on page 73, Table 39 on page 79, and Table 40 on page 79 for USART pin placement.
ATmega162/V AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers • Baud Rate Generation • Transmitter Operation • Transmit Buffer Functionality • Receiver Operation However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two buffer registers operate as a circular FIFO buffer.
Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Internal clock generation is used for the asynchronous and the synchronous master modes of operation.
ATmega162/V Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication.
Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • 5, 6, 7, 8, or 9 data bits • no, even or odd parity bit • 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit.
ATmega162/V If used, the parity bit is located between the last data bit and first stop bit of a serial frame. USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage.
Baud and Control Registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the transmitter’s serial output.
ATmega162/V Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16.
Empty Interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXC) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
ATmega162/V Receiving Frames with 5 to 8 Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When the first stop bit is received, i.e.
Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change.
ATmega162/V The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer.
Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits.
ATmega162/V (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 79. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated.
Figure 81. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FE) Flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting.
ATmega162/V Table 71. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max. Total Error (%) Recommended Max. Receiver Error (%) 5 93.20 106.67 +6.67/-6.8% ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.7 /-3.83 ± 1.5 Table 72.
The Multi-processor Communication mode enables several slave MCUs to receive data from a Master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. Using MPCM For an MCU to act as a Master MCU, it can use a 9-bit character frame format (UCSZ = 7).
ATmega162/V Accessing UBRRH/ UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated.
Read Access Doing a read access to the UBRRH or the UCSRC Register is a more complex operation. However, in most applications, it is rarely necessary to read any of these registers. The read access is controlled by a timed sequence. Reading the I/O location once returns the UBRRH Register contents. If the register location was read in previous system clock cycle, reading the register in the current clock cycle will return the UCSRC contents.
ATmega162/V USART Register Description USART I/O Data Register – UDR Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDR (Read) TXB[7:0] UDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location.
UDRE is set after a Reset to indicate that the transmitter is ready. • Bit 4 – FE: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA.
ATmega162/V • Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE Flag. A Data Register Empty interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA is set. • Bit 4 – RXEN: Receiver Enable Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxD pin when enabled.
USART Control and Status Register C – UCSRC(1) Bit 7 6 5 4 3 2 1 0 URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 0 0 0 0 1 1 0 Note: UCSRC 1. The UCSRC Register shares the same I/O location as the UBRRH Register. See the “Accessing UBRRH/ UCSRC Registers” on page 183 section which describes how to access this register.
ATmega162/V • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size) in a frame the receiver and transmitter use. Table 76. UCSZ Bits Settings UCSZ2 UCSZ1 UCSZ0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOL: Clock Polarity This bit is used for synchronous mode only.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
ATmega162/V Table 79. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.
Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.
ATmega162/V Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.
Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega162/V the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
JTAG Interface and On-chip Debug System Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega162/V The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming.
Figure 84.
ATmega162/V TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 84 depend on the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test-Logic-Reset. As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
Using the On-chip Debug As shown in Figure 83, the hardware support for On-chip Debugging consists mainly of system • A scan chain on the interface between the internal AVR CPU and the internal peripheral units • Break Point unit • Communication interface between the CPU and JTAG system All read or modify/write operations needed for implementing the Debugger are done by applying AVR instructions via the internal AVR CPU Scan Chain.
ATmega162/V On-chip debug specific JTAG instructions The On-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected 3rd party vendors only. Instruction opcodes are listed for reference. PRIVATE0; 0x8 Private JTAG instruction for accessing On-chip debug system. PRIVATE1; 0x9 Private JTAG instruction for accessing On-chip debug system. PRIVATE2; 0xA Private JTAG instruction for accessing On-chip debug system.
Bibliography 202 For more information about general Boundary-scan, the following literature can be consulted: • IEEE: IEEE Std. 1149.1-1990.
ATmega162/V IEEE 1149.1 (JTAG) Boundary-scan Features • • • • • System Overview The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register.
Data Registers The data registers relevant for Boundary-scan operations are: • Bypass Register • Device Identification Register • Reset Register • Boundary-scan Chain Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested.
ATmega162/V on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out Period (refer to “Clock Sources” on page 34) after releasing the Reset Register. The output from this data register is not latched, so the reset will take place immediately, as shown in Figure 86. Figure 86.
IDCODE; 0x1 Optional JTAG instruction selecting the 32-bit ID-register as data register. The ID-Register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after Power-up. The active states are: SAMPLE_PRELOAD; 0x2 • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input.
ATmega162/V If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to one. The reason for this is to avoid static current at the TDO pin in the JTAG interface. • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.
Figure 87. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
ATmega162/V Figure 88.
Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low Frequency Crystal Oscillator, and Ceramic Resonator. Figure 90 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock output is attached to an observe-only cell.
ATmega162/V Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 91. The Boundary-scan cell from Figure 92 is attached to each of these signals. The signals are described in Table 87. The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 91. Analog Comparator BANDGAP REFERENCE ACBG ACO AC_IDLE Figure 92.
Table 87.
ATmega162/V Table 88. ATmega162 Boundary-scan Order (Continued) Bit Number Signal Name Module 87 PB5.Data Port B 86 PB5.Control 85 PB5.Pullup_Enable 84 PB6.Data 83 PB6.Control 82 PB6.Pullup_Enable 81 PB7.Data 80 PB7.Control 79 PB7.Pullup_Enable 78 RSTT 77 RSTHV 76 TOSC 75 TOSCON 74 PD0.Data 73 PD0.Control 72 PD0.Pullup_Enable 71 PD1.Data 70 PD1.Control 69 PD1.Pullup_Enable 68 PD2.Data 67 PD2.Control 66 PD2.Pullup_Enable 65 PD3.Data 64 PD3.Control 63 PD3.
Table 88. ATmega162 Boundary-scan Order (Continued) 214 Bit Number Signal Name Module 51 PD7.Pullup_Enable Port D 50 EXTCLKEN 49 OSCON Enable signals for main Clock/Oscillators 48 OSC32EN 47 EXTCLK (XTAL1) 46 OSCCK 45 OSC32CK 44 PC0.Data 43 PC0.Control 42 PC0.Pullup_Enable 41 PC1.Data 40 PC1.Control 39 PC1.Pullup_Enable 38 PC2.Data 37 PC2.Control 36 PC2.Pullup_Enable 35 PC3.Data 34 PC3.Control 33 PC3.Pullup_Enable 32 PE2.Data 31 PE2.Control 30 PE2.
ATmega162/V Table 88. ATmega162 Boundary-scan Order (Continued) Bit Number Signal Name Module 15 PA5.Pullup_Enable Port A 14 PA4.Data 13 PA4.Control 12 PA4.Pullup_Enable 11 PA3.Data 10 PA3.Control 9 PA3.Pullup_Enable 8 PA2.Data 7 PA2.Control 6 PA2.Pullup_Enable 5 PA1.Data 4 PA1.Control 3 PA1.Pullup_Enable 2 PA0.Data 1 PA0.Control 0 PA0.Pullup_Enable Note: Boundary-scan Description Language Files 1. PRIVATE_SIGNAL1 should always be scanned in as zero.
Boot Loader Support – Read-While-Write Self-programming The Boot Loader Support provides a real Read-While-Write Self-programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega162/V Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update.
Figure 94.
ATmega162/V ming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock (Lock bit mode 1) does not control reading nor writing by LPM/SPM, if it is attempted. Table 90. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section.
Entering the Boot Loader Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interProgram face. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code.
ATmega162/V • Bit 3 – BLBSET: Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles.
Addressing the Flash During Selfprogramming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 106 on page 235), the Program Counter can be treated as having two different sections.
ATmega162/V Self-programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page 56.
ATmega162/V executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Bit 7 6 5 4 3 2 1 0 Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1 The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCR.
3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCR Register and thus the Flash from unintentional writes. Programming Time for Flash When Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 93 shows the typical programming time for Flash accesses from the CPU. Table 93.
ATmega162/V ldi looplo, low(PAGESIZEB) ldi loophi, high(PAGESIZEB) subi YL, low(PAGESIZEB) sbci YH, high(PAGESIZEB) Rdloop: lpm r0, Z+ ld r1, Y+ cpse r0, r1 jmp Error sbiw loophi:looplo, 1 brne Rdloop ;init loop variable ;not required for PAGESIZEB<=256 ;restore pointer ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ; ready yet ret ; re-enable the RWW section ldi spmcrval, (
ATmega162 Boot Loader Parameters In Table 94 through Table 96, the parameters used in the description of the self programming are given. Table 94.
ATmega162/V Table 96. Explanation of Different Variables Used in Figure 95 and the Mapping to the Z-pointer(1) Corresponding Z-value Variable PCMSB 12 Most significant bit in the Program Counter. (The Program Counter is 13 bits PC[12:0]) 5 Most significant bit which is used to address the words within one page (64 words in a page requires 6 bits PC [5:0]). PAGEMSB Z13 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
Memory Programming Program And Data Memory Lock Bits The ATmega162 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 98. The Lock bits can only be erased to “1” with the Chip Erase command. Table 97.
ATmega162/V Table 98. Lock Bit Protection Modes(1)(2) (Continued) Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
Table 100. Fuse High Byte Fuse Low Byte Bit no Description Default Value OCDEN(3) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(4) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega162/V Latching of Fuses The Fuse values are latched when the device enters Programming mode and changes of the Fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The Fuses are also latched on Power-up in Normal mode. Signature Bytes All Atmel microcontrollers have a 3-byte signature code which identifies the device.
Table 102.
ATmega162/V Table 105. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse Bits 0010 0000 Write Lock Bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock Bits 0000 0010 Read Flash 0000 0011 Read EEPROM Table 106. No. of Words in a Page and no. of Pages in the Flash Flash Size 8K words (16K bytes) Page Size PCWORD No.
Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash or EEPROM are reprogrammed. Note: 1. The EEPRPOM memory is preserved during chip erase if the EESAVE Fuse is programmed. Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”.
ATmega162/V While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 97 on page 237. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. G. Load Address High byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”.
Figure 98. Programming the Flash Waveforms F A DATA 0x10 B ADDR. LOW C D E DATA LOW DATA HIGH XX B ADDR. LOW C DATA LOW D DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: Programming the EEPROM “XX” is don’t care. The letters refer to the programming description above. The EEPROM is organized in pages, see Table 107 on page 235. When programming the EEPROM, the program data is latched into a page buffer.
ATmega162/V Figure 99. Programming the EEPROM Waveforms K A DATA 0x11 G ADDR. HIGH B ADDR. LOW C E DATA XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 236 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4.
Programming the Fuse High Bits The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” on page 236 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte.
ATmega162/V Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 236 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock Bits by any external Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
Reading the Calibration Byte The algorithm for reading the calibration byte is as follows (refer to “Programming the Flash” on page 236 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. Parallel Programming Characteristics Figure 102.
ATmega162/V Figure 104. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (low byte) ADDR1 (low byte) DATA (high byte) DATA (low byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 102 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 108.
Table 108. Parallel Programming Characteristics, VCC = 5 V ± 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: Min Max Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse Bits and Write Lock Bits commands. 2. tWLRH_CE is valid for the Chip Erase command. Serial Downloading SPI Serial Programming Pin Mapping Table 109.
ATmega162/V Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz SPI Serial Programming Algorithm When writing serial data to the ATmega162, data is clocked on the rising edge of SCK.
6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF.
ATmega162/V Table 111. SPI Serial Programming Instruction Set(1) Instruction Programming Enable Chip Erase Instruction Format Operation Byte 1 Byte 2 Byte 3 Byte4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming after RESET goes low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0010 H000 00aa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
Table 111. SPI Serial Programming Instruction Set(1) (Continued) Instruction Instruction Format Operation Byte 1 Byte 2 Byte 3 Byte4 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. “0” = programmed, “1” = unprogrammed. See Table 100 on page 232 for details. 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = pro-grammed, “1” = unprogrammed. See Table 99 on page 231 for details.
ATmega162/V Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the Reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the Fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low.
Figure 107.
ATmega162/V AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as data register. Note that the reset will be active as long as there is a logic “one” in the Reset Chain. The output from this chain is not latched.
Data Registers The Data Registers are selected by the JTAG Instruction Registers described in section “Programming Specific JTAG Instructions” on page 249. The Data Registers relevant for programming operations are: • Reset Register Reset Register • Programming Enable Register. • Programming Command Register. • Virtual Flash Page Load Register. • Virtual Flash Page Read Register. The Reset Register is a test data register used to reset the part during programming.
ATmega162/V Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 112. The state sequence when shifting in the programming commands is illustrated in Figure 110. Figure 109.
Table 112. JTAG Programming Instruction Set Instruction TDI sequence TDO sequence 1a. Chip eRase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2d.
ATmega162/V Table 112. JTAG Programming Instruction Set (Continued) Instruction TDI sequence TDO sequence 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. Write Fuse Extended Byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d.
Table 112. JTAG Programming Instruction Set (Continued) Instruction TDI sequence TDO sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse ext. byte Fuse high byte Fuse low byte Lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 9c.
ATmega162/V Figure 110. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR Virtual Flash Page Load Register 1 Exit1-IR 0 1 0 1 Exit1-DR 0 1 Update-IR 0 1 0 The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page.
Figure 111. Virtual Flash Page Load Register STROBES State Machine ADDRESS TDI Flash EEPROM Fuses Lock Bits D A T A TDO Virtual Flash Page Read Register 258 The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus eight. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte-by-byte.
ATmega162/V Figure 112. Virtual Flash Page Read Register STROBES State Machine ADDRESS TDI Flash EEPROM Fuses Lock Bits D A T A TDO Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 112. Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift one in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2.
8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH_FLASH (refer to Table 108 on page 243). 9. Repeat steps 3 to 7 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b and 2c.
ATmega162/V Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed. See “Performing Chip Erase” on page 259. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address high byte using programming instruction 4b. 4. Load address low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7.
Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8f. To only read Fuse Extended byte, use programming instruction 8b. To only read Fuse High byte, use programming instruction 8c. To only read Fuse Low byte, use programming instruction 8d. To only read Lock bits, use programming instruction 8e. Reading the Signature Bytes 1.
ATmega162/V Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units Active 1 MHz, VCC = 2V (ATmega162V) 0.8 mA Active 4 MHz, VCC = 3V (ATmega162/V) 5 mA Active 8 MHz, VCC = 5V (ATmega162) 16 mA Idle 1 MHz, VCC = 2V (ATmega162V) 0.3 mA Idle 4 MHz, VCC = 3V (ATmega162/V) 2 mA Idle 8 MHz, VCC = 5V (ATmega162) 8 mA Power Supply Current ICC Power-down mode WDT Enabled, VCC = 3.0V < 10 14 µA WDT Disabled, VCC = 3.0V < 1.
ATmega162/V Figure 113. Absolute Maximum Frequency as a function of VCC, ATmega162V Frequency 16 MHz 8 MHz Safe Operating Area 1 MHz VCC 1.8V 2.4V 2.7V 4.5V 5.5V Figure 114. Absolute Maximum Frequency as a function of VCC, ATmega162 Frequency 16 MHz 8 MHz Safe Operating Area 1 MHz VCC 1.8V 2.4V 2.7V 4.5V 5.
External Clock Drive Waveforms Figure 115. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 113. External Clock Drive VCC = 1.8 - 5.5V 266 VCC =2.7 - 5.5V VCC = 4.5 - 5.5V Symbol Parameter Min. Max. Min. Max. Min. Max. Units 1/tCLCL Oscillator Frequency 0 1 0 8 0 16 MHz tCLCL Clock Period 1000 125 62.5 ns tCHCX High Time 400 50 25 ns tCLCX Low Time 400 50 25 ns tCLCH Rise Time 2.0 1.6 0.5 µs tCHCL Fall Time 2.0 1.6 0.
ATmega162/V SPI Timing Characteristics See Figure 116 and Figure 117 for details. Table 114. SPI Timing Parameters Description Mode 1 SCK period Master See Table 68 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 117. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 268 MSB 17 ...
ATmega162/V External Data Memory Timing Table 115. External Data Memory Characteristics, 4.5 - 5.5 Volts, no Wait-state 8 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 1 tLHLL ALE Pulse Width 115 1.0tCLCL-10 ns 2 tAVLL Address Valid A to ALE Low 57.5 0.
Table 117. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 4 MHz Oscillator Min Max Variable Oscillator Symbol Parameter Min Max Unit 0 1/tCLCL Oscillator Frequency 0.0 16 MHz 10 tRLDV Read Low to Data Valid 12 tRLRH RD Pulse Width 365 3.0tCLCL-10 ns 15 tDVWH Data Valid to WR High 375 3.0tCLCL ns 16 tWLWH WR Pulse Width 365 3.0tCLCL-10 ns 325 3.0tCLCL-50 ns Table 118. External Data Memory Characteristics, 4.5 - 5.
ATmega162/V Table 119. External Data Memory Characteristics, 2.7 - 5.5 Volts, no Wait-state (Continued) 4 MHz Oscillator 12 Symbol Parameter Min tRLRH RD Pulse Width 235 Max Variable Oscillator Min Max 1.0tCLCL-15 Unit ns (1) 13 tDVWL Data Setup to WR Low 105 14 tWHDX Data Hold After WR High 235 1.0tCLCL-15 ns 15 tDVWH Data Valid to WR High 250 1.0tCLCL ns 16 tWLWH WR Pulse Width 235 1.0tCLCL-15 ns Notes: 0.5tCLCL-20 ns 1. This assumes 50% clock duty cycle.
Figure 118. External Memory Timing (SRWn1 = 0, SRWn0 = 0 T1 T2 T3 T4 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 DA7:0 Prev. data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Data 5 Read Address 11 10 8 12 RD Figure 119. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Prev. addr. Address 15 3a DA7:0 Prev.
ATmega162/V Figure 120. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T5 T4 T6 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 DA7:0 Prev. data 3a Address 13 XX Data 14 16 6 Write 2 WR 9 3b DA7:0 (XMBK = 0) Address 11 5 Read Data 10 8 12 RD Figure 121. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T4 T6 T5 T7 System Clock (CLKCPU ) 1 ALE 4 A15:8 7 Address Prev. addr. 15 Prev.
ATmega162 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with railto-rail output is used as clock source. The CKSEL Fuses are programmed to select external clock. The power consumption in Power-down mode is independent of clock selection.
ATmega162/V Figure 123. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1- 20 MHz ICC (mA) 45 40 5.5V 35 5.0V 30 4.5V 25 4.0V 20 15 3.3V 10 2.7V 5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 124. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. V CC INTERNAL RC OSCILLATOR, 8 MHz 20 18 85°C 25°C -40°C 16 14 ICC (mA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 125. Active Supply Current vs. VCC (32 kHz External Oscillator) ACTIVE SUPPLY CURRENT vs. V CC 32kHz EXTERNAL OSCILLATOR 300 250 25°C 85°C ICC (uA) 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 126. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 1.2 5.5V 1 5.0V ICC (mA) 0.8 4.5V 0.6 4.0V 3.3V 0.4 2.7V 0.2 1.8V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega162/V Figure 127. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 25 5.5V 20 5.0V 15 ICC (mA) 4.5V 10 4.0V 3.3V 5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 128. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 9 85°C 25°C -40°C 8 7 ICC (mA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 129. Idle Supply Current vs. VCC (32 kHz External Oscillator) IDLE SUPPLY CURRENT vs. VCC 32kHz EXTERNAL OSCILLATOR 70 60 85°C 25°C ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 130. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. V CC WATCHDOG TIMER DISABLED 3 85°C 2.5 ICC (uA) 2 1.5 1 -40°C 25°C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega162/V Figure 131. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. V CC WATCHDOG TIMER ENABLED 25 85°C 20 25°C -40°C ICC (uA) 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 132. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs. V CC WATCHDOG TIMER DISABLED 30 85°C 25°C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Standby Supply Current Figure 133. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 455 kHz RESONATOR, WATCHDOG TIMER DISABLED 70 60 ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 134. Standby Supply Current vs. V CC (1 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. V CC 1 MHz RESONATOR, WATCHDOG TIMER DISABLED 60 50 ICC (uA) 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega162/V Figure 135. Standby Supply Current vs. V CC (2 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 2 MHz XTAL, WATCHDOG TIMER DISABLED 90 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 136. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 2 MHz XTAL, WATCHDOG TIMER DISABLED 90 80 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 137. Standby Supply Current vs. V CC (4 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 4 MHz RESONATOR, WATCHDOG TIMER DISABLED 140 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 138. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 4 MHz XTAL, WATCHDOG TIMER DISABLED 140 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega162/V Figure 139. Standby Supply Current vs. V CC (6 MHz Resonator, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 6 MHz RESONATOR, WATCHDOG TIMER DISABLED 180 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 140. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC 6 MHz XTAL, WATCHDOG TIMER DISABLED 200 180 160 140 ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Pin Pull-up Figure 141. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 160 85°C 140 25°C 120 -40°C IIO (uA) 100 80 60 40 20 0 0 1 2 3 4 6 5 VIO (V) Figure 142. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 80 85°C 25°C 70 -40°C 60 IIO (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega162/V Figure 143. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 1.8V 60 50 85°C 25°C IOP (uA) 40 -40°C 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 144. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs.
Figure 145. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 60 -40°C 25°C 50 85°C IRESET (uA) 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 146. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 1.8V 40 -40°C 35 25°C 30 85°C IRESET (uA) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega162/V Pin Driver Strength Figure 147. I/O Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 80 -40°C 70 25°C IOH (mA) 60 85°C 50 40 30 20 10 0 0 1 2 3 4 5 6 VOH (V) Figure 148. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 30 -40°C 25 25°C 85°C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.
Figure 149. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) -40°C I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 8 25°C 7 85°C 6 IOH (mA) 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) Figure 150. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 90 -40°C 80 70 25°C IOL (mA) 60 85°C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega162/V Figure 151. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 35 -40°C 30 25°C IOL (mA) 25 85°C 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 152. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 12 -40°C 10 25°C 8 IOL (mA) 85°C 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Pin Thresholds and Hysteresis Figure 153. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) I/O PIN INPUT THRESHOLD VOLTAGE vs. V CC VIH, I/O PIN READ AS '1' 3 85°C 25°C -40°C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 154. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, I/O PIN READ AS '0' 3 85°C 25°C -40°C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.
ATmega162/V Figure 155. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. VCC 0.6 -40°C 0.5 25°C Threshold (V) 0.4 85°C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 156. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 3 2.5 Threshold (V) 2 -40°C 1.5 25°C 85°C 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 157. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 2.5 Threshold (V) 2 1.5 1 0.5 85°C 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 158. Reset Input Pin Hysteresis vs. VCC RESET INPUT PIN HYSTERESIS vs. VCC 0.7 -40°C 0.6 Threshold (V) 0.5 25°C 0.4 0.3 85°C 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega162/V BOD Thresholds and Analog Comparator Offset Figure 159. BOD Thresholds vs. Temperature (BOD Level is 4.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3V 4.6 4.5 Rising VCC Threshold (V) 4.4 Falling VCC 4.3 4.2 4.1 4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 90 100 Temperature (˚C) Figure 160. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 3 2.9 Rising VCC Threshold (V) 2.8 Falling VCC 2.7 2.6 2.
Figure 161. BOD Thresholds vs. Temperature (BOD Level is 2.3V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.3V 2.6 2.5 Rising VCC Threshold (V) 2.4 Falling VCC 2.3 2.2 2.1 2 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 90 100 Temperature (˚C) Figure 162. BOD Thresholds vs. Temperature (BOD Level is 1.8V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8V 2.1 2 Rising VCC Threshold (V) 1.9 1.8 Falling VCC 1.7 1.6 1.
ATmega162/V Figure 163. Bandgap Voltage vs. VCC BANDGAP VOLTAGE vs. VCC 1.14 Bandgap Voltage (V) 1.13 1.12 1.11 85°C 25°C -40°C 1.1 1.09 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 164. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5V 0.01 85°C Comparator Offset Voltage (V) 0.009 25°C 0.008 -40°C 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
Figure 165. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7V 0.006 85°C Comparator Offset Voltage (V) 0.005 25°C 0.004 -40°C 0.003 0.002 0.001 0 -0.001 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Internal Oscillator Speed Figure 166. Watchdog Oscillator Frequency vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1300 -40°C 25°C 85°C 1250 FRC (kHz) 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.
ATmega162/V Figure 167. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.4 5.5V 4.0V 2.7V 1.8V 8.3 8.2 FRC (MHz) 8.1 8 7.9 7.8 7.7 7.6 7.5 -60 -40 -20 0 20 40 60 80 100 Ta (˚C) Figure 168. Calibrated 8 MHz RC Oscillator Frequency vs.VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 10 9.5 9 FRC (MHz) 8.5 85°C 25°C 8 -40°C 7.5 7 6.5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 169. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 16 14 FRC (MHz) 12 10 8 6 4 0 16 32 48 64 80 96 112 OSCCAL VALUE Current Consumption of Peripheral Units Figure 170. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 35 -40°C 85°C 25°C 30 25 ICC (uA) 20 15 10 5 0 -5 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega162/V Figure 171. 32 kHz TOSC Current vs. VCC (Watchdog Timer Disabled) 32kHz TOSC CURRENT vs. VCC WATCHDOG TIMER DISABLED 30 85°C 25°C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 172. Watchdog TImer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 20 85°C 25°C -40°C 18 16 14 ICC (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 173. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 80 70 -40°C 60 25°C 85°C ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 174. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc 25 -40°C 20 25°C ICC (mA) 15 85°C 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega162/V Current Consumption in Reset and Reset Pulsewidth Figure 175. Reset Supply Current vs. Frequency (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 4.5 5.5V ICC (mA) 4 3.5 5.0V 3 4.5V 4.0V 2.5 3.3V 2 2.7V 1.5 1.8V 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 176. Reset Supply Current vs.
Figure 177. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. VCC 2500 Pulsewidth (ns) 2000 1500 1000 500 85°C 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega162/V Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xFF) Reserved – – – – – – – – Page ..
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x60) Reserved – – – – – – – – 0x3F (0x5F) SREG I T H S V N Z C 8 0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 11 SP6 SP5 SP4 SP3 SP2 SP1 UBRR1[11:8] SP0 0x3D (0x5D) (2) (2) 0x3C (0x5C) 0x3B (0x5B) Page SPL SP7 UBRR1H URSEL1 11 UCSR1C URSEL1 UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 188 GICR INT1 INT0 INT2 PCIE1 PCIE0 – IVSEL IVCE 60, 85 189 0x3A (0x5A)
ATmega162/V Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x01 (0x21) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 186 0x00 (0x20) UBRR1L Notes: USART1 Baud Rate Register Low Byte 189 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC.
Instruction Set Summary Mnemonics Operands Description Flags Operation #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd
ATmega162/V Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 Rd ← Rr Rd+1:Rd ← Rr+1:Rr None 1 None 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd ← K None LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc.
Mnemonics Operands CLH Description Operation Clear Half Carry Flag in SREG H←0 Flags #Clocks H 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr.
ATmega162/V Ordering Information Speed (MHz) 8(3) 16(4) Notes: Ordering Code Package(1) Operation Range 1.8 - 5.5V ATmega162V-8AI ATmega162V-8PI ATmega162V-8MI ATmega162V-8AU(2) ATmega162V-8PU(2) ATmega162V-8MU(2) 44A 40P6 44M1 44A 40P6 44M1 Industrial (-40°C to 85°C) 2.7 - 5.5V ATmega162-16AI ATmega162-16PI ATmega162-16MI ATmega162-16AU(2) ATmega162-16PU(2) ATmega162-16MU(2) 44A 40P6 44M1 44A 40P6 44M1 Industrial (-40°C to 85°C) Power Supply 1.
Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.
ATmega162/V 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.
44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 b K Option C e b 0.25 REF 0.18 D Pin #1 Notch (0.20 R) BOTTOM VIEW D2 5.00 0.30 5.20 5.40 7.00 BSC 5.00 e Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. 0.23 7.00 BSC E E2 NOTE 5.20 5.40 0.
ATmega162/V Erratas The revision letter in this section refers to the revision of the ATmega162 device. ATmega162, all rev. There are no errata for this revision of ATmega162. However, a proposal for solving problems regarding the JTAG instruction IDCODE is presented below. IDCODE masks data from TDI input The public but optional JTAG instruction IDCODE is not implemented correctly according to IEEE1149.
Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 2513F-09/03 to Rev. 2513G-03/05 1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”. 2. Updated “Electrical Characteristics” on page 263 3. Updated “Ordering Information” on page 309 Changes from Rev. 2513D-04/03 to Rev. 2513E-09/03 1.
ATmega162/V 10. Added note under “Filling the Temporary Buffer (Page Loading)” on page 223 about writing to the EEPROM during an SPM Page Load. 11. Added section “EEPROM Write During Power-down Sleep Mode” on page 22. 12. Added information about PWM symmetry for Timer0 on page 97 and Timer2 on page 146. 13. Updated Table 18 on page 47, Table 20 on page 49, Table 36 on page 76, Table 83 on page 204, Table 110 on page 246, Table 113 on page 266, and Table 114 on page 267. 14.
ATmega162/V Table of Contents Features................................................................................................ 1 Pin Configurations............................................................................... 2 Disclaimer ............................................................................................................. 2 Overview............................................................................................... 3 Block Diagram ..............................
Extended Standby Mode .................................................................................... 43 Minimizing Power Consumption ......................................................................... 44 System Control and Reset ................................................................ 46 Internal Voltage Reference ................................................................................. 51 Watchdog Timer ...........................................................................
ATmega162/V Overview........................................................................................................... Timer/Counter Clock Sources........................................................................... Counter Unit...................................................................................................... Output Compare Unit........................................................................................ Compare Match Output Unit ................................
Data Registers .................................................................................................. Boundary-scan Specific JTAG Instructions ...................................................... Boundary-scan Chain ....................................................................................... ATmega162 Boundary-scan Order................................................................... Boundary-scan Description Language Files .....................................................
ATmega162/V Erratas .............................................................................................. 313 ATmega162, all rev........................................................................................... 313 Datasheet Revision History ............................................................ 314 Changes from Rev. 2513F-09/03 to Rev. 2513G-03/05 ................................... Changes from Rev. 2513D-04/03 to Rev. 2513E-09/03 ...................................
vi ATmega162/V 2513G–AVR–03/05
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