Datasheet

295
2466T–AVR–07/10
ATmega16(L)
5. This requirement applies to all ATmega16 Two-wire Serial Interface operation. Other devices
connected to the Two-wire Serial Bus need only obey the general f
SCL
requirement.
Figure 146. Two-wire Serial Bus Timing
SPI Timing
Characteristics
See Figure 147 and Figure 148 for details.
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r
Table 121. SPI Timing Parameters
Description Mode Min Typ Max
1 SCK period Master See Table 58
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 • t
SCK
7 SCK to out Master 10
8 SCK to out high Master 10
9SS low to out Slave 15
10 SCK period Slave 4 • t
SCK
11 SCK high/low Slave 2 • t
SCK
12 Rise/Fall time Slave 1.6 µs
13 Setup Slave 10
ns
14 Hold Slave 10
15 SCK to out Slave 15
16 SCK to SS
high Slave 20
17 SS
high to tri-state Slave 10
18 SS low to SCK Slave 2 • t
SCK