Datasheet

166
2466T–AVR–07/10
ATmega16(L)
• Bit 0 – TXB8: Transmit Data Bit 8
TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDR.
USART Control and
Status Register C –
UCSRC
The UCSRC Register shares the same I/O location as the UBRRH Register. See the “Accessing
UBRRH/ UCSRC Registers” on page 162 section which describes how to access this register.
• Bit 7 – URSEL: Register Select
This bit selects between accessing the UCSRC or the UBRRH Register. It is read as one when
reading UCSRC. The URSEL must be one when writing the UCSRC.
• Bit 6 – UMSEL: USART Mode Select
This bit selects between Asynchronous and Synchronous mode of operation.
• Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.
If a mismatch is detected, the PE Flag in UCSRA will be set.
• Bit 3 – USBS: Stop Bit Select
This bit selects the number of Stop Bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Bit 76543210
URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL UCSRC
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value10000110
Table 63. UMSEL Bit Settings
UMSEL Mode
0 Asynchronous Operation
1 Synchronous Operation
Table 64. UPM Bits Settings
UPM1 UPM0 Parity Mode
0 0 Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 65. USBS Bit Settings
USBS Stop Bit(s)
01-bit
12-bit