Datasheet

126
2466T–AVR–07/10
ATmega16(L)
Timer/Counter
Timing Diagrams
The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk
T2
)
is therefore shown as a clock enable signal. In Asynchronous mode, clk
I/O
should be replaced by
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set. Figure 60 contains timing data for basic Timer/Counter operation. The figure shows the
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 60. Timer/Counter Timing Diagram, no Prescaling
Figure 61 shows the same timing data, but with the prescaler enabled.
Figure 61. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 62 shows the setting of OCF2 in all modes except CTC mode.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)