Features • High-performance, Low-power Atmel® AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 16 Kbytes of In-System Self-programmable Flash program memory – 512 Bytes EEPROM – 1 Kbyte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,
ATmega16(L) Pin Configurations Figure 1.
ATmega16(L) Overview The ATmega16 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2.
ATmega16(L) The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega16(L) Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega16(L) Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention 1. Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
ATmega16(L) About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documentation for more details.
ATmega16(L) AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3.
ATmega16(L) Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16-bit or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection.
ATmega16(L) • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic.
ATmega16(L) General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega16(L) The X-register, Yregister and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5.
ATmega16(L) Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept.
ATmega16(L) 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 45 for more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write SelfProgramming” on page 246. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
ATmega16(L) When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
ATmega16(L) AVR ATmega16 Memories This section describes the different memories in the ATmega16. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega16 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. In-System Reprogrammable Flash Program Memory The ATmega16 contains 16 Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega16(L) SRAM Data Memory Figure 9 shows how the ATmega16 SRAM Memory is organized. The lower 1120 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
ATmega16(L) Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10. Figure 10. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address Valid Write Data WR Read Data RD Memory Access Instruction EEPROM Data Memory Next Instruction The ATmega16 contains 512 bytes of data EEPROM memory.
ATmega16(L) The EEPROM Address Register – EEARH and EEARL Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 – – – – – – – EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits 15..9 – Res: Reserved Bits These bits are reserved bits in the ATmega16 and will always read as zero. • Bits 8..0 – EEAR8..
ATmega16(L) • Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2.
ATmega16(L) also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
ATmega16(L) The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
ATmega16(L) EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC Reset Protection circuit can be used.
ATmega16(L) System Clock and Clock Options Clock Systems and their Distribution Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 32. The clock systems are detailed Figure 11. Figure 11.
ATmega16(L) ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 2.
ATmega16(L) choosing capacitors for use with crystals are given in Table 4. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 12. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4. Table 4. Crystal Oscillator Operating Modes CKOPT CKSEL3..
ATmega16(L) The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5. Table 5. Start-up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1..0 Start-up Time from Power-down and Power-save 0 00 258 CK(1) 4.1 ms Ceramic resonator, fast rising power 0 01 258 CK(1) 65 ms Ceramic resonator, slowly rising power 0 10 1K CK(2) – Ceramic resonator, BOD enabled 0 11 1K CK(2) 4.
ATmega16(L) Low-frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should be connected as shown in Figure 12. By programming the CKOPT Fuse, the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The internal capacitors have a nominal value of 36 pF.
ATmega16(L) When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8. Table 8. Start-up Times for the External RC Oscillator Clock Selection SUT1..0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) 00 18 CK – 01 18 CK 4.1 ms Fast rising power 10 18 CK 65 ms Slowly rising power 11 6 CK(1) 4.1 ms Fast rising power or BOD enabled Note: Recommended Usage BOD enabled 1.
ATmega16(L) Oscillator Calibration Register – OSCCAL Bit Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7..0 – CAL7..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the Internal Oscillator to remove process variations from the Oscillator frequency. This is done automatically during Chip Reset.
ATmega16(L) External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 14. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between XTAL1 and GND. Figure 14. External Clock Drive Configuration EXTERNAL CLOCK SIGNAL When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 12. Table 12.
ATmega16(L) Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed.
ATmega16(L) Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
ATmega16(L) Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. Extended Standby Mode When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode.
ATmega16(L) Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
ATmega16(L) JTAG Interface and On-chip Debug System If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: • Disable OCDEN Fuse. • Disable JTAGEN Fuse. • Write one to the JTD bit in MCUCSR.
ATmega16(L) System Control and Reset Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega16(L) Figure 15. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Control and Status Register (MCUCSR) Power-on Reset Circuit INTERNAL RESET Brown-out Reset Circuit BODEN BODLEVEL SPIKE FILTER Reset Circuit JTAG Reset Register Watchdog Timer COUNTER RESET Pull-up Resistor Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] Table 15. Reset Characteristics Symbol VPOT Parameter Condition Min Typ Max Power-on Reset Threshold Voltage (rising) 1.
ATmega16(L) Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 15. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on.
ATmega16(L) External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 15) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the Time-out period tTOUT has expired. Figure 18.
ATmega16(L) Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 42 for details on operation of the Watchdog Timer. Figure 20. Watchdog Reset During Operation CC CK MCU Control and Status Register – MCUCSR The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
ATmega16(L) Internal Voltage Reference ATmega16 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference to the ADC is generated from the internal bandgap reference. Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 16.
ATmega16(L) Watchdog Timer Control Register – WDTCR Bit 7 6 5 4 3 2 1 0 – – – WDTOE WDE WDP2 WDP1 WDP0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 WDTCR • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega16 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled.
ATmega16(L) The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega16(L) Interrupts Interrupt Vectors in ATmega16 This section describes the specifics of the interrupt handling as performed in ATmega16. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. Table 18. Reset and Interrupt Vectors Vector No.
ATmega16(L) Table 19. Reset and Interrupt Vectors Placement(1) BOOTRST IVSEL Reset address Interrupt Vectors Start Address 1 0 $0000 $0002 1 1 $0000 Boot Reset Address + $0002 0 0 Boot Reset Address $0002 0 1 Boot Reset Address Boot Reset Address + $0002 Note: 1. The Boot Reset Address is shown in Table 100 on page 257. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
ATmega16(L) When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2 Kbytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code $000 RESET: ldi r16,high(RAMEND) ; Main program start out SPH,r16 $001 $002 ldi Comments ; Set Stack Pointer to top of RAM r16,low(RAMEND) $003 out $004 sei SPL,r16 $005 ; Enable interrupts xxx ; .
ATmega16(L) Moving Interrupts Between Application and Boot Space General Interrupt Control Register – GICR The General Interrupt Control Register controls the placement of the Interrupt Vector table. Bit 7 6 5 4 3 2 1 0 INT1 INT0 INT2 – – – IVSEL IVCE Read/Write R/W R/W R/W R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GICR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory.
ATmega16(L) .
ATmega16(L) I/O Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega16(L) Figure 23. General Digital I/O(1) PUD Q D DDxn Q CLR RESET WDx Q Pxn D PORTxn Q CLR WPx DATA BUS RDx RESET RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: Configuring the Pin PULLUP DISABLE SLEEP CONTROL I/O CLOCK WDx: RDx: WPx: RRx: RPx: WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports.
ATmega16(L) Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 20 summarizes the control signals for the pin value. Table 20. Port Pin Configurations Reading the Pin Value DDxn PORTxn PUD (in SFIOR) I/O Pull-up 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low.
ATmega16(L) When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 25.
ATmega16(L) The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ...
ATmega16(L) Unconnected pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega16(L) Table 21 summarizes the function of the overriding signals. The pin and port indexes from Figure 26 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 21. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATmega16(L) Special Function I/O Register – SFIOR Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 51 for more details about this feature.
ATmega16(L) Table 24. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA2/ADC2 PA1/ADC1 PA0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT AIO Alternate Functions of Port B PA3/ADC3 The Port B pins with alternate functions are shown in Table 25. Table 25.
ATmega16(L) • MOSI – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit. • SS – Port B, Bit 4 SS: Slave Select input.
ATmega16(L) Table 26. Overriding Signals for Alternate Functions in PB7..
ATmega16(L) Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 28. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. Table 28.
ATmega16(L) • SDA – Port C, Bit 1 SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.
ATmega16(L) Table 30. Overriding Signals for Alternate Functions in PC3..PC0(1) Signal Name PC3/TMS PC2/TCK PC1/SDA PC0/SCL PUOE JTAGEN JTAGEN TWEN TWEN PUOV 1 1 PORTC1 • PUD PORTC0 • PUD DDOE JTAGEN JTAGEN TWEN TWEN DDOV 0 0 SDA_OUT SCL_OUT PVOE 0 0 TWEN TWEN PVOV 0 0 0 0 DIEOE JTAGEN JTAGEN 0 0 DIEOV 0 0 0 0 DI – – – – AIO TMS TCK SDA INPUT SCL INPUT Note: Alternate Functions of Port D 1.
ATmega16(L) • OC1A – Port D, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. • OC1B – Port D, Bit 4 OC1B, Output Compare Match B output: The PD4 pin can serve as an external output for the Timer/Counter1 Output Compare B.
ATmega16(L) Table 33. Overriding Signals for Alternate Functions in PD3..
ATmega16(L) Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Bit 7 6 5 4 3 2 1 0 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0
ATmega16(L) Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Bit 7 6 5 4 3 2 1 0 PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 Read/Write R/W R/W R/W R/W R
ATmega16(L) External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt).
ATmega16(L) • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 35. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt.
ATmega16(L) and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 interrupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled.
ATmega16(L) 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 27.
ATmega16(L) Unit” on page 73. for details. The compare match event will also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt request. Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise form must be used, that is, TCNT0 for accessing Timer/Counter0 counter value and so on.
ATmega16(L) whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 76.
ATmega16(L) The OCR0 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0 Buffer Register, and if double buffering is disabled the CPU will access the OCR0 directly. Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0) bit.
ATmega16(L) Figure 30. Compare Match Output Unit, Schematic COMn1 COMn0 FOCn Waveform Generator D Q 1 OCn DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0) from the Waveform Generator if either of the COM01:0 bits are set. However, the OC0 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATmega16(L) Modes of Operation The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM01:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega16(L) the double buffering feature. If the new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM01:0 = 1).
ATmega16(L) In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM01:0 to 3 (See Table 40 on page 84). The actual OC0 value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega16(L) Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC0) is cleared on the compare match between TCNT0 and OCR0 while upcounting, and set on the compare match while downcounting.
ATmega16(L) PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = ----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega16(L) Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 34 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 34.
ATmega16(L) Figure 36. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode. Figure 37.
ATmega16(L) 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Bit 7 6 5 4 3 2 1 0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0 • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode.
ATmega16(L) When OC0 is connected to the pin, the function of the COM01:0 bits depends on the WGM01:0 bit setting. Table 39 shows the COM01:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 39. Compare Output Mode, non-PWM Mode COM01 COM00 Description 0 0 Normal port operation, OC0 disconnected.
ATmega16(L) • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 42. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge.
ATmega16(L) • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR.
ATmega16(L) Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O).
ATmega16(L) sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 39.
ATmega16(L) 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement.
ATmega16(L) Figure 40. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATABUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: Registers TCCRnB 1.
ATmega16(L) The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 201.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes.
ATmega16(L) Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the Low byte triggers the 16-bit read or write operation.
ATmega16(L) The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega16(L) The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega16(L) Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 41 shows a block diagram of the counter and its surroundings. Figure 41. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega16(L) Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.
ATmega16(L) For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 92. Input Capture Pin Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit.
ATmega16(L) Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an output compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed.
ATmega16(L) temporary register (TEMP). However, it is a good practice to read the Low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The High byte (OCR1xH) has to be written first. When the High byte I/O location is written by the CPU, the TEMP Register will be updated by the value written.
ATmega16(L) Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega16(L) Modes of Operation The mode of operation, that is, the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega16(L) An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature.
ATmega16(L) Figure 46. Fast PWM Mode, Timing Diagram OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set OCnA Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value.
ATmega16(L) The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ---------------------------------N ⋅ ( 1 + TOP ) The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle.
ATmega16(L) Figure 47. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM.
ATmega16(L) the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 ⋅ N ⋅ TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega16(L) Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM).
ATmega16(L) output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures.
ATmega16(L) will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 51.
ATmega16(L) 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior.
ATmega16(L) Table 45. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 Note: COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM13:0 settings, normal port operation, OCnA/OCnB disconnected. 1 0 Clear OC1A/OC1B on compare match, set OC1A/OC1B at BOTTOM, (non-inverting mode) 1 1 Set OC1A/OC1B on compare match, clear OC1A/OC1B at BOTTOM, (inverting mode) 1.
ATmega16(L) A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 47.
ATmega16(L) Timer/Counter1 Control Register B – TCCR1B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered.
ATmega16(L) If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting.
ATmega16(L) The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP).
ATmega16(L) • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location.
ATmega16(L) 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module.
ATmega16(L) The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC2). See “Output Compare Unit” on page 119. for details. The compare match event will also set the Compare Flag (OCF2) which can be used to generate an output compare interrupt request.
ATmega16(L) bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not.
ATmega16(L) to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly.
ATmega16(L) Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The Waveform Generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next compare match. Also, the COM21:0 bits control the OC2 pin output source. Figure 56 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega16(L) Modes of Operation The mode of operation, that is, the behavior of the Timer/Counter and the output compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
ATmega16(L) value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output.
ATmega16(L) In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0 to 3 (see Table 52 on page 129). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega16(L) Figure 59. Phase Correct PWM Mode, Timing Diagram OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set TCNTn OCn (COMn1:0 = 2) OCn (COMn1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin.
ATmega16(L) Timer/Counter Timing Diagrams The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In Asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 60 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.
ATmega16(L) Figure 62. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn - 1 OCRn OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 63.
ATmega16(L) 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR2 Bit 7 6 5 4 3 2 1 0 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR2 • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode.
ATmega16(L) When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 51 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 51. Compare Output Mode, non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected.
ATmega16(L) • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 54. Table 54. Clock Select Bit Description Timer/Counter Register – TCNT2 CS22 CS21 CS20 0 0 0 No clock source (Timer/Counter stopped).
ATmega16(L) Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR Bit 7 6 5 4 3 2 1 0 – – – – AS2 TCN2UB OCR2UB TCR2UB Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a Crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin.
ATmega16(L) • The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency. • When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1.
ATmega16(L) 1. Write any value to either of the registers OCR2 or TCCR2. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. • Timer/Counter Interrupt Mask Register – TIMSK During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag.
ATmega16(L) Figure 64. Prescaler for Timer/Counter2 clkT2S PSR2 clkT2S/1024 clkT2S/256 clkT2S/8 AS2 clkT2S/128 10-BIT T/C PRESCALER Clear TOSC1 clkT2S/64 clkI/O clkT2S/32 Timer/Counter Prescaler 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
ATmega16(L) Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega16 and peripheral devices or between several AVR devices.
ATmega16(L) byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line.
ATmega16(L) Note: See “Alternate Functions of Port B” on page 58 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins.
ATmega16(L) Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
ATmega16(L) The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega16(L) SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs except MISO which can be user configured as an output, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega16(L) • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle.
ATmega16(L) SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
ATmega16(L) Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 67 and Figure 68. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 56 and Table 57, as done below: Table 59.
ATmega16(L) USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device.
ATmega16(L) The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The clock generation logic consists of synchronization logic for external clock input used by synchronous Slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by Synchronous Transfer mode.
ATmega16(L) Figure 70. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UMSEL 1 xcko DDR_XCK txclk 1 UCPOL 1 rxclk 0 Signal description: Internal Clock Generation – The Baud Rate Generator txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (Internal Signal). Used for synchronous Slave operation.
ATmega16(L) Table 60.
ATmega16(L) Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 71. Synchronous Mode XCK Timing.
ATmega16(L) IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0, and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.
ATmega16(L) Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<
ATmega16(L) frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the Baud Register, U2X bit or by XCK depending on mode of operation. The following code examples show a simple USART transmit function based on polling of the Data Register Empty (UDRE) Flag.
ATmega16(L) Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the Low byte of the character is written to UDR. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in Registers R17:R16.
ATmega16(L) The Transmit Complete (TXC) Flag bit is set one when the entire frame in the transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location.
ATmega16(L) Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the receiver is enabled, the normal pin operation of the RxD pin is overridden by the USART and given the function as the receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCK pin will be used as transfer clock.
ATmega16(L) Receiving Frames with 9 Databits If 9 bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and PE status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will change the state of the receive buffer FIFO and consequently the TXB8, FE, DOR and PE bits, which all are stored in the FIFO, will change.
ATmega16(L) The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer.
ATmega16(L) Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXEN is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The receiver buffer FIFO will be flushed when the receiver is disabled.
ATmega16(L) figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit.
ATmega16(L) Asynchronous Operational Range The operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see Table 61) base frequency, the receiver will not be able to synchronize the frames to the start bit.
ATmega16(L) Table 62. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2X = 1) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 8 96.00 103.90 +3.90/-4.00 ±1.5 9 96.39 103.53 +3.53/-3.61 ±1.5 10 96.70 103.23 +3.23/-3.30 ±1.0 The recommendations of the maximum receiver baud rate error was made under the assumption that the receiver and transmitter equally divides the maximum total error.
ATmega16(L) Multi-processor Communication Mode Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a filtering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus.
ATmega16(L) Accessing UBRRH/ UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated.
ATmega16(L) The following code example shows how to read the UCSRC Register contents. Assembly Code Example(1) USART_ReadUCSRC: ; Read UCSRC in r16,UBRRH in r16,UCSRC ret C Code Example(1) unsigned char USART_ReadUCSRC( void ) { unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; } Note: 1. See “About Code Examples” on page 7. The assembly code example returns the UCSRC value in r16.
ATmega16(L) USART Control and Status Register A – UCSRA Bit 7 6 5 4 3 2 1 0 RXC TXC UDRE FE DOR PE U2X MPCM Read/Write R R/W R R R R R/W R/W Initial Value 0 0 1 0 0 0 0 0 UCSRA • Bit 7 – RXC: USART Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (that is, does not contain any unread data).
ATmega16(L) • Bit 0 – MPCM: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode. When the MPCM bit is written to one, all the incoming frames received by the USART receiver that do not contain address information will be ignored. The transmitter is unaffected by the MPCM setting. For more detailed information see “Multi-processor Communication Mode” on page 161.
ATmega16(L) • Bit 0 – TXB8: Transmit Data Bit 8 TXB8 is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDR. USART Control and Status Register C – UCSRC Bit 7 6 5 4 3 2 1 0 URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 0 0 0 0 1 1 0 UCSRC The UCSRC Register shares the same I/O location as the UBRRH Register.
ATmega16(L) • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character Size) in a frame the Receiver and Transmitter use. Table 66. UCSZ Bits Settings UCSZ2 UCSZ1 UCSZ0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOL: Clock Polarity This bit is used for Synchronous mode only.
ATmega16(L) • Bit 11:0 – UBRR11:0: USART Baud Rate Register This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four most significant bits, and the UBRRL contains the 8 least significant bits of the USART baud rate. Ongoing transmissions by the transmitter and receiver will be corrupted if the baud rate is changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
ATmega16(L) Table 69. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.
ATmega16(L) Table 70. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.
ATmega16(L) Table 71. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.
ATmega16(L) Two-wire Serial Interface Features • • • • • • • • • • Two-wire Serial Interface Bus Definition The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines.
ATmega16(L) Electrical Interconnection As depicted in Figure 76, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero.
ATmega16(L) Figure 78. START, REPEATED START, and STOP Conditions SDA SCL START Address Packet Format REPEATED START STOP START STOP All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
ATmega16(L) Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA line high, a NACK is signalled.
ATmega16(L) Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several Masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more Masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the Masters to complete the transmission.
ATmega16(L) Figure 83. Arbitration between Two Masters START SDA from Master A Master A Loses Arbitration, SDAA SDA SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur.
ATmega16(L) Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 84. All registers drawn in a thick line are accessible through the AVR data bus. Figure 84.
ATmega16(L) or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Register is not directly accessible by the application software. However, when receiving, it can be set or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the value of the received (N)ACK bit can be determined by the value in the TWSR.
ATmega16(L) TWI Register Description TWI Bit Rate Register – TWBR Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TWBR • Bits 7..0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
ATmega16(L) is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. • Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.
ATmega16(L) • Bits 1..0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 73. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see “Bit Rate Generator Unit” on page 178. The value of TWPS1..0 is used in the equation.
ATmega16(L) • Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the Two-wire Serial Bus. Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
ATmega16(L) desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the address packet. 4.
ATmega16(L) Assembly code example 1 ldi r16, (1<
ATmega16(L) Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other Masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used.
ATmega16(L) A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value 1 X 1 0 X 1 0 X TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free.
ATmega16(L) Table 74.
ATmega16(L) Figure 87.
ATmega16(L) Figure 88. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER ........ Device 3 R1 Device n R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value 1 X 1 0 X 1 0 X TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
ATmega16(L) Table 75.
ATmega16(L) Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter (see Figure 90). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 90. Data Transfer in Slave Receiver Mode VCC Device 1 Device 2 SLAVE RECEIVER MASTER TRANSMITTER Device 3 ........
ATmega16(L) Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes.
ATmega16(L) Table 76.
ATmega16(L) Figure 91. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
ATmega16(L) The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address. TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI.
ATmega16(L) Table 77.
ATmega16(L) Figure 93. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted.
ATmega16(L) Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated 2. The EEPROM must be instructed what location should be read 3. The reading must be performed 4. The transfer must be finished Note that data is transmitted both from Master to Slave and vice versa.
ATmega16(L) Several different scenarios may arise during arbitration, as described below: • Two or more Masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the Masters will know about the bus contention. • Two or more Masters are accessing the same Slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits.
ATmega16(L) Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega16(L) Analog Comparator Control and Status Register – ACSR Bit 7 6 5 4 3 2 1 0 ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 ACSR • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in active and Idle mode.
ATmega16(L) Table 79. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed.
ATmega16(L) Analog to Digital Converter Features • • • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 13 µs- 260 µs Conversion Time Up to 15 kSPS at Maximum Resolution 8 Multiplexed Single Ended Input Channels 7 Differential Input Channels 2 Differential Input Channels with Optional Gain of 10x and 200x Optional Left adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
ATmega16(L) Figure 98. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] TRIGGER SELECT ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADATE ADEN ADSC MUX1 15 ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX3 MUX2 MUX4 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS AVCC PRESCALER START GAIN SELECTION CHANNEL SELECTION MUX DECODER CONVERSION LOGIC INTERNAL 2.
ATmega16(L) becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.
ATmega16(L) Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
ATmega16(L) will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 81. Figure 101.
ATmega16(L) Figure 103. ADC Timing Diagram, Auto Triggered Conversion One Conversion Cycle Number 1 2 3 4 5 6 7 8 9 Next Conversion 10 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 104.
ATmega16(L) all single conversions, and the first free running conversion) when CKADC2 is low will take the same amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC clock cycles due to the synchronization mechanism.
ATmega16(L) ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
ATmega16(L) sleep modes and the user wants to perform differential conversions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an extended conversion to get a valid result. Analog Input Circuitry The Analog Input Circuitry for single ended channels is illustrated in Figure 105. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC.
ATmega16(L) PA3 (ADC3) PA2 (ADC2) PA1 (ADC1) PA0 (ADC0) VCC GND Figure 106. ADC Power Connections PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) GND AVCC 100 nF AREF 10 µH PA7 (ADC7) PC7 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs.
ATmega16(L) Figure 107. Offset Error Output Code Ideal ADC Actual ADC Offset Error • VREF Input Voltage Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 108.
ATmega16(L) Figure 109. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF • Input Voltage Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 110.
ATmega16(L) ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN ⋅ 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 83 on page 217 and Table 84 on page 218). 0x000 represents ground, and 0x3FF represents the selected reference voltage minus one LSB.
ATmega16(L) Table 82. Correlation between Input Voltage and Output Codes VADCn Read code Corresponding Decimal Value VADCm + VREF/GAIN 0x1FF 511 VADCm + 511/512 VREF/GAIN 0x1FF 511 VADCm + 510/512 VREF/GAIN 0x1FE 510 ... ... ... VADCm + 1/512 VREF/GAIN 0x001 1 VADCm 0x000 0 VADCm - 1/512 VREF/GAIN 0x3FF -1 ... ... ... VADCm - 511/512 VREF/GAIN 0x201 -511 VADCm - VREF/GAIN 0x200 -512 Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.
ATmega16(L) sions. For a complete description of this bit, see “The ADC Data Register – ADCL and ADCH” on page 220. • Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 84 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). Table 84.
ATmega16(L) Table 84. Input Channel and Gain Selections (Continued) MUX4..0 Single Ended Input 11101 ADC Control and Status Register A – ADCSRA 11110 1.
ATmega16(L) Table 85.
ATmega16(L) Special FunctionIO Register – SFIOR Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 7:5 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect.
ATmega16(L) JTAG Interface and On-chip Debug System Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega16(L) The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming.
ATmega16(L) Figure 113. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR TAP Controller 1 Exit1-IR 0 1 0 1 1 0 1 Update-IR 0 1 0 The TAP controller is a 16-state finite state machine that controls the operation of the Boundaryscan circuitry, JTAG programming circuitry, or On-chip Debug system.
ATmega16(L) on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The ExitIR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.
ATmega16(L) A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 226. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip Debug system to work.
ATmega16(L) On-chip Debug Related Register in I/O Memory On-chip Debug Register – OCDR Bit 7 6 5 4 3 2 1 MSB/IDRD 0 LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location.
ATmega16(L) IEEE 1149.1 (JTAG) Boundary-scan Features • • • • • System Overview The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register.
ATmega16(L) controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. Device Identification Register Figure 114 shows the structure of the Device Identification Register. Figure 114. The Format of the Device Identification Register MSB Bit Device ID Version 31 LSB 28 27 12 11 1 0 Version Part Number Manufacturer ID 1 4 bits 16 bits 11 bits 1 bit Version is a 4-bit number identifying the revision of the component.
ATmega16(L) Figure 115. Reset Register To TDO From other Internal and External Reset Sources From TDI D Q Internal Reset ClockDR · AVR_RESET Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connections. See “Boundary-scan Chain” on page 232 for a complete description.
ATmega16(L) The active states are: AVR_RESET; $C • Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. • Shift-DR: The Boundary-scan Chain is shifted by the TCK input. • Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However, the output latches are not connected to the pins. The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG Reset source.
ATmega16(L) Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connection. Scanning the Digital Port Pins Figure 116 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function.
ATmega16(L) Figure 117.
ATmega16(L) Figure 118. Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn TWIEN Pxn SRC Slew-rate Limited IDxn Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel Programming. An observe-only cell as shown in Figure 119 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV. Figure 119.
ATmega16(L) Figure 120. Boundary-scan Cells for Oscillators and Clock Options To Next Cell From Digital Logic ShiftDR XTAL2/TOSC2 Oscillator EXTEST To Next Cell ShiftDR 0 ENABLE OUTPUT 1 FF1 0 D Q D Q 0 1 D G From Previous Cell ClockDR To System Logic XTAL1/TOSC1 Q 1 UpdateDR From Previous Cell ClockDR Table 90 summaries the scan registers for the external clock pin XTAL1, Oscillators with XTAL1/XTAL2 connections as well as 32 kHz Timer Oscillator. Table 90.
ATmega16(L) Figure 121. Analog Comparator BANDGAP REFERENCE ACBG ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 122.
ATmega16(L) Table 91.
ATmega16(L) Table 92.
ATmega16(L) Table 92.
ATmega16(L) controlling/observing any ADC signal, or perform a dummy conversion before using the first result. • The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode). As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC.
ATmega16(L) ATmega16 Boundary-scan Order Table 94 shows the scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
ATmega16(L) Table 94. ATmega16 Boundary-scan Order (Continued) Bit Number Signal Name 111 MUXEN_6 110 MUXEN_5 109 MUXEN_4 108 MUXEN_3 107 MUXEN_2 106 MUXEN_1 105 MUXEN_0 104 NEGSEL_2 103 NEGSEL_1 102 NEGSEL_0 101 PASSEN 100 PRECH 99 SCTEST 98 ST 97 VCCREN 96 PB0.Data 95 PB0.Control 94 PB0.Pullup_Enable 93 PB1.Data 92 PB1.Control 91 PB1.Pullup_Enable 90 PB2.Data 89 PB2.Control 88 PB2.Pullup_Enable 87 PB3.Data 86 PB3.Control 85 PB3.Pullup_Enable 84 PB4.
ATmega16(L) Table 94. ATmega16 Boundary-scan Order (Continued) Bit Number Signal Name Module 75 PB7.Data 74 PB7.Control 73 PB7.Pullup_Enable 72 RSTT 71 RSTHV 70 EXTCLKEN 69 OSCON 68 RCOSCEN 67 OSC32EN 66 EXTCLK (XTAL1) 65 OSCCK 64 RCCK 63 OSC32CK 62 TWIEN TWI 61 PD0.Data Port D 60 PD0.Control 59 PD0.Pullup_Enable 58 PD1.Data 57 PD1.Control 56 PD1.Pullup_Enable 55 PD2.Data 54 PD2.Control 53 PD2.Pullup_Enable 52 PD3.Data 51 PD3.Control 50 PD3.
ATmega16(L) Table 94. ATmega16 Boundary-scan Order (Continued) Bit Number Signal Name 39 PD7.Control 38 PD7.Pullup_Enable 37 PC0.Data 36 PC0.Control 35 PC0.Pullup_Enable 34 PC1.Data 33 PC1.Control 32 PC1.Pullup_Enable 31 PC6.Data 30 PC6.Control 29 PC6.Pullup_Enable 28 PC7.Data 27 PC7.Control 26 PC7.Pullup_Enable 25 TOSC 24 TOSCON 23 PA7.Data 22 PA7.Control 21 PA7.Pullup_Enable 20 PA6.Data 19 PA6.Control 18 PA6.Pullup_Enable 17 PA5.Data 16 PA5.
ATmega16(L) Table 94. ATmega16 Boundary-scan Order (Continued) Bit Number Signal Name 4 PA1.Control 3 PA1.Pullup_Enable 2 PA0.Data 1 PA0.Control 0 PA0.Pullup_Enable Notes: Boundary-scan Description Language Files Module 1. PRIVATE_SIGNAL1 should always be scanned in as zero. 2. PRIVATE:SIGNAL2 should always be scanned in as zero. Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software.
ATmega16(L) Boot Loader Support – ReadWhile-Write SelfProgramming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
ATmega16(L) RWW – Read-WhileWrite Section If a Boot Loader software update is programming a page inside the RWW section, it is possible to read code from the Flash, but only code that is located in the NRWW section. During an ongoing programming, the software must ensure that the RWW section never is being read. If the user software is trying to read code that is located inside the RWW section (that is, by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state.
ATmega16(L) Figure 125.
ATmega16(L) Table 96. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
ATmega16(L) Table 98. Boot Reset Fuse(1) BOOTRST Note: Store Program Memory Control Register – SPMCR Reset Address 1 Reset Vector = Application reset (address $0000) 0 Reset Vector = Boot Loader reset (see Table 100 on page 257) 1. “1” means unprogrammed, “0” means programmed The Store Program Memory Control Register contains the control bits needed to control the Boot Loader operations.
ATmega16(L) • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a page write, or if no SPM instruction is executed within four clock cycles.
ATmega16(L) Figure 126. Addressing the Flash during SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: Self-Programming the Flash 1. The different variables used in Figure 126 are listed in Table 102 on page 258. 2. PCPAGE and PCWORD are listed in Table 107 on page 262.
ATmega16(L) Performing Page Erase by SPM Filling the Temporary Buffer (Page Loading) To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer must be written zero during this operation. • Page Erase to the RWW section: The NRWW section can be read during the page erase.
ATmega16(L) Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCR and execute SPM within four clock cycles after writing SPMCR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any software update by the MCU.
ATmega16(L) A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1.
ATmega16(L) Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during self-programming (page erase and page write).
ATmega16(L) sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ; ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega16(L) Table 102. Explanation of Different Variables used in Figure 126 and the Mapping to the Zpointer Corresponding Z-value(1) Variable PCMSB 12 Most significant bit in the Program Counter. (The Program Counter is 13 bits PC[12:0]) 5 Most significant bit which is used to address the words within one page (64 words in a page requires 6 bits PC [5:0]). PAGEMSB Z13 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals PCMSB + 1.
ATmega16(L) Memory Programming Program And Data Memory Lock Bits The ATmega16 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 104. The Lock bits can only be erased to “1” with the Chip Erase command. Table 103.
ATmega16(L) Table 104. Lock Bit Protection Modes (Continued) Memory Lock Bits(2) BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega16(L) Table 106. Fuse Low Byte Fuse Low Byte Bit No.
ATmega16(L) Page Size Table 107. No. of Words in a Page and no. of Pages in the Flash Flash Size 8K words (16 Kbytes) Page Size PCWORD No. of Pages PCPAGE PCMSB 64 words PC[5:0] 128 PC[12:6] 12 Table 108. No. of Words in a Page and no. of Pages in the EEPROM EEPROM Size Page Size PCWORD No.
ATmega16(L) Table 109.
ATmega16(L) Table 112.
ATmega16(L) Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5V - 5.5V between VCC and GND, and wait at least 100 µs. 2. Set RESET to “0” and toggle XTAL1 at least 6 times 3. Set the Prog_enable pins listed in Table 110 on page 263 to “0000” and wait at least 100 ns. 4. Apply 11.5V - 12.5V to RESET.
ATmega16(L) Programming the Flash The Flash is organized in pages, see Table 107 on page 262. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4.
ATmega16(L) I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 128.
ATmega16(L) Figure 129. Programming the Flash Waveforms(1) F A DATA $10 B C ADDR. LOW DATA LOW D DATA HIGH E B C D E G XX ADDR. LOW DATA LOW DATA HIGH XX ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: Programming the EEPROM 1. “XX” is don’t care. The letters refer to the programming description above. The EEPROM is organized in pages, see Table 108 on page 262. When programming the EEPROM, the program data is latched into a page buffer.
ATmega16(L) Figure 130. Programming the EEPROM Waveforms K A DATA 0x11 G B ADDR. HIGH ADDR. LOW C E B C E DATA XX ADDR. LOW DATA XX L XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 266 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High Byte ($00 - $FF) 3. B: Load Address Low Byte ($00 - $FF) 4.
ATmega16(L) Programming the Fuse High Bits The algorithm for programming the Fuse high bits is as follows (refer to “Programming the Flash” on page 266 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte. Figure 131.
ATmega16(L) Figure 132. Mapping between BS1, BS2 and the Fuse- and Lock Bits during Read 0 Fuse Low Byte DATA Lock Bits 0 1 BS1 Fuse High Byte 1 BS2 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 266 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte ($00 - $02). 3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA. 4.
ATmega16(L) Figure 134. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 133 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 135.
ATmega16(L) Table 113.
ATmega16(L) Figure 136. SPI Serial Programming and Verify(1) +2.7 - 5.5V VCC +2.7 - 5.5V(2) MOSI PB5 MISO PB6 SCK PB7 AVCC XTAL1 RESET GND Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC -0.3V < AVCC < VCC +0.3V, however, AVCC should always be within 2.7V - 5.
ATmega16(L) 4. The Flash is programmed one page at a time. The page size is found in Table 107 on page 262. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data Low byte must be loaded before data High byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 7 MSB of the address.
ATmega16(L) Table 115. Minimum Wait Delay before Writing the Next Flash or EEPROM Location Serial Programming Instruction set Symbol Minimum Wait Delay tWD_FUSE 4.5 ms tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms Table 116 on page 276 and Figure 137 on page 277 describes the Instruction set. Table 116.
ATmega16(L) Notes: 1. 2. 3. 4. 5. Not all instructions are applicable for all parts. a = address Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.
ATmega16(L) SPI Serial Programming Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 295. Figure 138. SPI Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI and TDO. Control of the reset and clock pins is not required.
ATmega16(L) Figure 139. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR AVR_RESET ($C) 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset Mode.
ATmega16(L) PROG_COMMANDS ($5) PROG_PAGELOAD ($6) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
ATmega16(L) Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering programming mode. A high value in the Reset Register corresponds to pulling the external Reset low. The part is reset as long as there is a high value present in the Reset Register.
ATmega16(L) Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 117. The state sequence when shifting in the programming commands is illustrated in Figure 142. Figure 141.
ATmega16(L) Table 117. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 1a. Chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for chip erase complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b.
ATmega16(L) Table 117. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c.
ATmega16(L) Table 117. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 11a. Load No Operation Command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx Notes: Notes 1.
ATmega16(L) Figure 142. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR Virtual Flash Page Load Register 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page.
ATmega16(L) Figure 143. Virtual Flash Page Load Register STROBES TDI State Machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO Virtual Flash Page Read Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte by byte.
ATmega16(L) Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 117. Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 2. Disable all programming instructions by using no operation instruction 11a. 3.
ATmega16(L) Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3.
ATmega16(L) Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data High byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. 4. Write Fuse High byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 113 on page 272). 6. Load data Low byte using programming instructions 6e.
ATmega16(L) Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATmega16(L) TA = -40°C to 85°C, VCC = 2.7V to 5.5V (Unless Otherwise Noted) (Continued) Symbol Parameter Power Supply Current ICC Power-down Mode(5) Condition Typ Max Active 1 MHz, VCC = 3V (ATmega16L) 1.1 Active 4 MHz, VCC = 3V (ATmega16L) 3.8 5 Active 8 MHz, VCC = 5V (ATmega16) 12 15 0.35 Idle 4 MHz, VCC = 3V (ATmega16L) 1.2 2 Idle 8 MHz, VCC = 5V (ATmega16) 5.
ATmega16(L) 5] The sum of all IOH, for ports D3 - D7, should not exceed 100 mA. 6] The sum of all IOH, for ports C0 - C7, should not exceed 100 mA.If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V. External Clock Drive Waveforms Figure 145. External Clock Drive Waveforms V IH1 V IL1 External Clock Drive Table 118. External Clock Drive(1) VCC = 2.7V to 5.
ATmega16(L) Two-wire Serial Interface Characteristics Table 120 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega16 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 146. Table 120. Two-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) Min Max Input Low-voltage -0.5 0.3 VCC Input High-voltage 0.
ATmega16(L) 5. This requirement applies to all ATmega16 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement. Figure 146. Two-wire Serial Bus Timing tHIGH tof tr tLOW tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF SPI Timing Characteristics See Figure 147 and Figure 148 for details. Table 121.
ATmega16(L) Figure 147. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 148. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ATmega16(L) ADC Characteristics Table 122. ADC Characteristics Symbol Parameter Resolution Condition Min(1) Typ(1) Single Ended Conversion 10 Differential Conversion Gain = 1x or 10x 8 Differential Conversion Gain = 200x 7 Max(1) Bits Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz 1.5 2.5 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1 MHz 3 4 Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200 kHz Noise Reduction mode 1.
ATmega16(L) Table 122. ADC Characteristics (Continued) Symbol Parameter Condition Min(1) Typ(1) Max(1) Units 2.3 2.6 2.9 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Notes: 1. Values are guidelines only. 2. Minimum for AVCC is 2.7V. 3. Maximum for AVCC is 5.5V.
ATmega16(L) ATmega16 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
ATmega16(L) Figure 150. Active Supply Current vs. Frequency (1 MHz - 20 MHz) 35 30 5.5V 25 5.0V ICC (mA) 4.5V 20 15 4.0V 3.6V 10 3.3V 3.0V 5 2.7V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 151. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 16 -40°C 14 25°C 85°C 12 ICC (mA) 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 152. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) 9 25°C 8 -40°C 7 85°C ICC (mA) 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 153. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) 4.5 25°C 4 85°C 3.5 -40°C ICC (mA) 3 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 154. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) 2.5 85°C 25°C 2 -40°C ICC (mA) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 155. Active Supply Current vs. VCC (32 kHz External Oscillator) 180 85°C 160 25°C 140 ICC (µA) 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Idle Supply Current Figure 156. Idle Supply Current vs. Frequency (0.1 MHz - 1.0 MHz) 0.8 5.5V 0.7 5.0V 0.6 4.5V ICC (mA) 0.5 4.0V 3.6V 3.3V 3.0V 2.7V 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 157. Idle Supply Current vs. Frequency (1 MHz - 20 MHz) 16 5.5V 14 5.0V 12 4.5V ICC (mA) 10 8 4.0V 6 3.6V 4 2 2.7V 3.3V 3.
ATmega16(L) Figure 158. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 8 25°C -40°C 7 85°C 6 ICC (mA) 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Oscillator, 4 MHz) Figure 159. Idle Supply Current vs. VCC (Internal RC , 4 -40°C 25°C 3.5 85°C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 160. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) 2 1.8 25°C 85°C 1.6 -40°C 1.4 ICC (mA) 1.2 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 161. Idle Supply Current vs. VCC (Internal RC , Oscillator, 1 MHz) 1 25°C 0.9 85°C 0.8 0.7 ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 162. Idle Supply Current vs. VCC (32 kHz External Oscillator) 40 85°C 25°C 35 30 ICC (µA) 25 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-Down Supply Current Figure 163. Power-Down Supply Current vs. VCC (Watchdog Timer Disabled) 2.5 85°C 2 -40°C 25°C ICC (µA) 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 164. Power-Down Supply Current vs. VCC (Watchdog Timer Enabled) 20 18 -40°C 85°C 16 25°C 14 ICC (µA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-Save Supply Current Figure 165. Power-Save Supply Current vs. VCC (Watchdog Timer Disabled) 18 85°C 16 25°C 14 ICC (µA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Standby Supply Current Figure 166. Standby Supply Current vs. VCC (455 kHz Resonator, Watchdog Timer Disabled) 60 50 ICC (µA) 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 167. Standby Supply Current vs. VCC (1 MHz Resonator, Watchdog Timer Disabled) 50 45 40 35 ICC (µA) 30 25 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 168. Standby Supply Current vs. VCC (2 MHz Resonator, Watchdog Timer Disabled) 80 70 60 ICC (µA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 169. Standby Supply Current vs. VCC (2 MHz Xtal, Watchdog Timer Disabled) 80 70 60 ICC (µA) 50 40 30 20 10 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 170. Standby Supply Current vs. VCC (4 MHz Resonator, Watchdog Timer Disabled) 120 100 ICC (µA) 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 171. Standby Supply Current vs. VCC (4 MHz Xtal, Watchdog Timer Disabled) 120 100 ICC (µA) 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 172. Standby Supply Current vs. VCC (6 MHz Resonator, Watchdog Timer Disabled) 140 120 ICC (µA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 173. Standby Supply Current vs. VCC (6 MHz Xtal, Watchdog Timer Disabled) 180 160 140 ICC (µA) 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Pin Pullup Figure 174. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 85°C 25°C 120 -40°C IIO (µA) 100 80 60 40 20 0 0 1 2 3 VIO (V) Figure 175. I/O Pin Pull-Up Resistor Current vs. Input Voltage (VCC = 2.7V) 100 90 80 85°C 25°C 70 IIO (µA) 60 -40°C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega16(L) Figure 176. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 25°C -40°C 100 85°C IRESET (µA) 80 60 40 20 0 0 1 2 3 VRESET (V) Figure 177. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 25°C -40°C 50 85°C IRESET (µA) 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega16(L) Pin Driver Strength Figure 178. I/O Pin Source Current vs. Output Voltage (VCC = 5V) 90 -40°C 80 25°C 70 85°C IOH (mA) 60 50 40 30 20 10 0 0 1 2 3 4 VOH (V) Figure 179. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) 30 -40°C 25 25°C 85°C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega16(L) Figure 180. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) 90 80 -40°C 70 25°C IOL (mA) 60 85°C 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 181. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) 35 -40°C 30 25°C 25 IOL (mA) 85°C 20 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega16(L) Pin Thresholds And Hysteresis Figure 182. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read As '1') 2.5 -40°C 25°C 2 Threshold (V) 85°C 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 183. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read As '0') 2.5 Threshold (V) 2 -40°C 1.5 25°C 85°C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 184. I/O Pin Input Hysteresis vs. VCC 0.8 85°C 25°C 0.6 Hysteresis (mV) -40°C 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 185. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read As '1') , 2.5 2 Threshold (V) -40°C 25°C 85°C 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 186. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read As '0') 2.5 Threshold (V) 2 1.5 85°C 25°C 1 -40°C 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 187. Reset Input Pin Hysteresis vs. VCC 0.5 -40°C 0.45 0.4 Hysteresis (mV) 0.35 0.3 25°C 0.25 0.2 0.15 85°C 0.1 0.05 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Bod Thresholds And Analog Comparator Offset Figure 188. Bod Thresholds vs. Temperature (Bodlevel is 4.0V) 4.1 4 Threshold (V) Rising VCC 3.9 3.8 Falling VCC 3.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 80 90 100 Temperature (°C) Figure 189. Bod Thresholds vs. Temperature (Bodlevel is 2.7V) 3 2.9 Rising VCC Threshold (V) 2.8 2.7 2.6 Falling VCC 2.5 2.
ATmega16(L) Figure 190. Bandgap Voltage vs. VCC 1.25 85° Bandgap Voltage (V) 1.245 25° -40° 1.24 1.235 1.23 1.225 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 191. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) 0 Comparator Offset Voltage (V) -0.001 -0.002 -0.003 -0.004 -0.005 -0.006 85°C -0.007 25°C -0.008 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega16(L) Figure 192. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 3V) 0 Comparator Offset Voltage (V) -0.001 -0.002 -0.003 -0.004 -0.005 85°C 25°C -0.006 -0.007 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Internal Oscillator Speed Figure 193. Watchdog Oscillator Frequency vs. VCC 1060 -40°C 25°C 1050 1040 85°C 1030 FRC (kHz) 1020 1010 1000 990 980 970 960 950 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 194. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 9 8.6 FRC (MHz) 8.2 5.5V 7.8 4.0V 7.4 7 2.7V 6.6 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 195. Calibrated 8 MHz RC Oscillator Frequency vs. VCC FRC (MHz) 8.5 8.3 -40°C 8.1 25°C 7.9 85°C 7.7 7.5 7.3 7.1 6.9 6.7 6.5 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 196. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value 13 12 11 FRC (MHz) 10 9 8 7 6 5 4 3 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 197. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature 4.1 4 FRC (MHz) 5.5V 3.9 4.0V 3.8 3.7 2.7V 3.
ATmega16(L) Figure 198. Calibrated 4 MHz RC Oscillator Frequency vs. VCC 4.2 4.1 -40°C 25°C FRC (MHz) 4 85°C 3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 199. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value 6.5 6 5.5 FRC (MHz) 5 4.5 4 3.5 3 2.5 2 1.
ATmega16(L) Figure 200. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature 2.1 2.05 FRC (MHz) 2 5.5V 1.95 4.0V 1.9 1.85 2.7V 1.8 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 201. Calibrated 2 MHz RC Oscillator Frequency vs. VCC 2.2 FRC (MHz) 2.1 -40°C 25°C 85°C 2 1.9 1.8 1.7 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 202. Calibrated 2 MHz RC Oscillator Frequency vs. Osccal Value 3.2 3 2.8 2.6 FRC (MHz) 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE Figure 203. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature 1.02 1.01 1 5.5V FRC (MHz) 0.99 0.98 0.97 4.0V 0.96 0.95 0.94 2.7V 0.
ATmega16(L) Figure 204. Calibrated 1 MHz RC Oscillator Frequency vs. VCC 1.1 FRC (MHz) 1.05 25°C 1 -40°C 85°C 0.95 0.9 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 205. Calibrated 1 MHz RC Oscillator Frequency vs. Osccal Value 1.6 1.4 FRC (MHz) 1.2 1 0.8 0.6 0.
ATmega16(L) Current Consumption Of Peripheral Units Figure 206. Brownout Detector Current vs. VCC 20 -40°C 18 25°C ICC (µA) 16 85°C 14 12 10 8 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 207. ADC Current vs. VCC(Aref = AVCC) 350 300 250 ICC (µA) 25°C 85°C -40°C 200 150 100 50 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 208. Aref External Reference Current vs. VCC 180 85°C 160 25°C 140 -40°C IAREF (µA) 120 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 209. 32khz Tosc Current vs. VCC (Watchdog Timer Disabled) 16 85°C 14 25°C 12 ICC (µA) 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Figure 210. Watchdog Timer Current vs. VCC 18 16 -40°C 25°C 14 85°C ICC (µA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 211. Programming Current vs. VCC 9 -40°C ICC (mA) 8 7 25°C 6 85°C 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
ATmega16(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $3F ($5F) SREG I T H S V N Z C 9 $3E ($5E) SPH – – – – – SP10 SP9 SP8 12 SP4 SP3 SP2 SP1 SP0 12 – – – IVSEL IVCE 48, 69 $3D ($5D) SPL $3C ($5C) OCR0 $3B ($5B) GICR SP7 SP6 SP5 Timer/Counter0 Output Compare Register INT1 INT0 Page 85 INT2 $3A ($5A) GIFR INTF1 INTF0 INTF2 – – – – – 70 $39 ($59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TO
ATmega16(L) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $01 ($21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 181 $00 ($20) TWBR Notes: Two-wire Serial Interface Bit Rate Register 180 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3.
ATmega16(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two R
ATmega16(L) Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd ← Rr Rd+1:Rd ← Rr+1:Rr LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc.
ATmega16(L) Mnemonics Operands CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK Flags Description Operation Clear Half Carry Flag in SREG H←0 H No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr.
ATmega16(L) Ordering Information Speed (MHz) Note: Power Supply Ordering Code Package 44A 40P6 44M1 Industrial (-40oC to 85oC) 44A 40P6 44M1 Industrial (-40oC to 85oC) 8 2.7V - 5.5V ATmega16L-8AU(1) ATmega16L-8PU(1) ATmega16L-8MU(1) 16 4.5V - 5.5V ATmega16-16AU(1) ATmega16-16PU(1) ATmega16-16MU(1) Operation Range 1. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
ATmega16(L) Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.
ATmega16(L) 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C eB Notes: COMMON DIMENSIONS (Unit of Measure = mm) REF 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.
ATmega16(L) 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig.
ATmega16(L) Errata The revision letter in this section refers to the revision of the ATmega16 device. ATmega16(L) Rev. M • • • • First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1.
ATmega16(L) Problem Fix/Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronized to the asynchronous timer clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00.
ATmega16(L) Problem Fix / Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx). 3. IDCODE masks data from TDI input The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are replaced by all-ones during Update-DR.
ATmega16(L) – If ATmega16 is the only device in the scan chain, the problem is not visible. – Select the Device ID Register of the ATmega16 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Issue the BYPASS instruction to the ATmega16 while reading the Device ID Registers of preceding devices of the boundary scan chain.
ATmega16(L) 4. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. ATmega16(L) Rev.
ATmega16(L) Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Rev. 2466T-07/10 1. Corrected use of comma in formula Rp in Table 120, “Two-wire Serial Bus Requirements,” on page 294. 2. Updated document according to Atmel’s Technical Terminology 3. Note 6 and Note 7 under Table 120, “Two-wire Serial Bus Requirements,” on page 294 have been removed. 1.
ATmega16(L) Rev. 2466N-10/06 1. Updated “Timer/Counter Oscillator” on page 31. 2. Updated “Fast PWM Mode” on page 102. 3. Updated Table 38 on page 83, Table 40 on page 84, Table 45 on page 111, Table 47 on page 112, Table 50 on page 128 and Table 52 on page 129. 4. Updated C code example in “USART Initialization” on page 149. 5. Updated “Errata” on page 340. Rev. 2466M-04/06 1. Updated typos. 2. Updated “Serial Peripheral Interface – SPI” on page 135. 3.
ATmega16(L) Rev. 2466G-10/03 1. Removed “Preliminary” from the datasheet. 2. Changed ICP to ICP1 in the datasheet. 3. Updated “JTAG Interface and On-chip Debug System” on page 36. 4. Updated assembly and C code examples in “Watchdog Timer Control Register – WDTCR” on page 43. 5. Updated Figure 46 on page 103. 6. Updated Table 15 on page 38, Table 82 on page 217 and Table 115 on page 276. 7. Updated “Test Access Port – TAP” on page 222 regarding JTAGEN. 8. Updated description for the JTD bit on page 231. 9.
ATmega16(L) 9. Added Table 73, “TWI Bit Rate Prescaler,” on page 182 to describe the TWPS bits in the “TWI Status Register – TWSR” on page 181. 10. Added section “Default Clock Source” on page 25. 11. Added note about frequency variation when using an external clock. Note added in “External Clock” on page 31. An extra row and a note added in Table 118 on page 293. 12. Various minor TWI corrections. 13. Added “Power Consumption” data in “Features” on page 1. 14.
ATmega16(L) 8. Added JTAG version number for rev. H in Table 87 on page 229. 9. Added not regarding OCDEN Fuse below Table 105 on page 260. 10. Updated Programming Figures: Figure 127 on page 262 and Figure 136 on page 274 are updated to also reflect that AVCC must be connected during Programming mode. Figure 131 on page 270 added to illustrate how to program the fuses. 11. Added a note regarding usage of the “PROG_PAGELOAD ($6)” on page 280 and “PROG_PAGEREAD ($7)” on page 280. 12.
ATmega16(L) Table of Contents Features 1 Pin Configurations 2 Disclaimer 2 Overview 3 Block Diagram 3 Pin Descriptions 4 Resources 6 Data Retention 6 About Code Examples 7 AVR CPU Core 8 Introduction 8 Architectural Overview 8 ALU – Arithmetic Logic Unit 9 Status Register 9 General Purpose Register File 11 Stack Pointer 12 Instruction Execution Timing 13 Reset and Interrupt Handling 13 AVR ATmega16 Memories 16 In-System Reprogrammable Flash Program Memory 16 SRAM Data Memory 17 EEPROM Data Memory 18 I/O M
Idle Mode 33 ADC Noise Reduction Mode 33 Power-down Mode 33 Power-save Mode 33 Standby Mode 34 Extended Standby Mode 34 Minimizing Power Consumption 35 System Control and Reset 37 Internal Voltage Reference 42 Watchdog Timer 42 Interrupts 45 Interrupt Vectors in ATmega16 45 I/O Ports 50 Introduction 50 Ports as General Digital I/O 50 Alternate Port Functions 55 Register Description for I/O Ports 66 External Interrupts 68 8-bit Timer/Counter0 with PWM 71 Overview 71 Timer/Counter Clock Sources 72 Counter
ATmega16(L) 8-bit Timer/Counter2 with PWM and Asynchronous Operation 117 Overview 117 Timer/Counter Clock Sources 118 Counter Unit 118 Output Compare Unit 119 Compare Match Output Unit 121 Modes of Operation 122 Timer/Counter Timing Diagrams 126 8-bit Timer/Counter Register Description 128 Asynchronous Operation of the Timer/Counter 131 Timer/Counter Prescaler 134 Serial Peripheral Interface – SPI 135 SS Pin Functionality 140 Data Modes 143 USART 144 Overview 144 Clock Generation 145 Frame Formats 148 USA
Prescaling and Conversion Timing 207 Changing Channel or Reference Selection 210 ADC Noise Canceler 211 ADC Conversion Result 216 JTAG Interface and On-chip Debug System 222 Features 222 Overview 222 Test Access Port – TAP 222 TAP Controller 224 Using the Boundary-scan Chain 225 Using the On-chip Debug System 225 On-chip Debug Specific JTAG Instructions 226 On-chip Debug Related Register in I/O Memory 227 Using the JTAG Programming Capabilities 227 Bibliography 227 IEEE 1149.
ATmega16(L) Electrical Characteristics 291 Absolute Maximum Ratings* 291 DC Characteristics 291 External Clock Drive Waveforms 293 External Clock Drive 293 Two-wire Serial Interface Characteristics 294 SPI Timing Characteristics 295 ADC Characteristics 297 ATmega16 Typical Characteristics 299 Register Summary 331 Instruction Set Summary 333 Ordering Information 336 Packaging Information 337 44A 337 40P6 338 44M1 339 Errata 340 ATmega16(L) Rev. M 340 ATmega16(L) Rev. L 340 ATmega16(L) Rev.
Rev. 2466E-10/02 348 Rev. 2466D-09/02 348 Rev.
ATmega16(L) vii 2466T–AVR–07/10
Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.
