Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 64 (9x9) 8-Bit 16 MHz I/O number 53

Features

• High-performance, Low-power Atmel

AVR

8-bit Microcontroller

• Advanced RISC Architecture

– 133 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers + Peripheral Control Registers

– Fully Static Operation

– Up to 16MIPS Throughput at 16MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 128KBytes of In-System Self-programmable Flash program memory

– 4KBytes EEPROM

– 4KBytes Internal SRAM

– Write/Erase cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Up to 64KBytes Optional External Memory Space

– Programming Lock for Software Security

– SPI Interface for In-System Programming

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and

Capture Mode

– Real Time Counter with Separate Oscillator

– Two 8-bit PWM Channels

– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits

– Output Compare Modulator

– 8-channel, 10-bit ADC

8 Single-ended Channels

7 Differential Channels

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x

– Byte-oriented Two-wire Serial Interface

– Dual Programmable Serial USARTs

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,

and Extended Standby

– Software Selectable Clock Frequency

– ATmega103 Compatibility Mode Selected by a Fuse

– Global Pull-up Disable

• I/O and Packages

– 53 Programmable I/O Lines

– 64-lead TQFP and 64-pad QFN/MLF

• Operating Voltages

– 2.7 - 5.5V

• Speed Grades

–0 - 16MHz

8-bit

Microcontroller

with 128KBytes

In-System

Programmable

Flash

ATmega128A

Summary

Rev. 8151HS–AVR–02/11

Summary of content (22 pages)

PAGE 1
Features • High-performance, Low-power Atmel®AVR®8-bit Microcontroller • Advanced RISC Architecture • • • • • • • – 133 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 128KBytes of In-System Self-programmable Flash program memory – 4KBytes EEPROM – 4KBytes Internal SRAM – Write/Erase cy
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1.
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ATmega128A Block Diagram PF0 - PF7 PA0 - PA7 PC0 - PC7 RESET Block Diagram XTAL2 Figure 2-1. XTAL1 2.1 VCC GND PORTA DRIVERS PORTF DRIVERS DATA DIR. REG. PORTF DATA REGISTER PORTF PORTC DRIVERS DATA DIR. REG. PORTA DATA REGISTER PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC CALIB.
PAGE 4
The Atmel®AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
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ATmega128A The Atmel®AVR®ATmega128A is 100% pin compatible with ATmega103, and can replace the ATmega103 on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128A” describes what the user should be aware of replacing the ATmega103 by an ATmega128A. 2.2.1 ATmega103 Compatibility Mode By programming the M103C fuse, the ATmega128 will be compatible with the ATmega103 regards to RAM, I/O pins and interrupt vectors as described above.
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2.3.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.
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ATmega128A JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. The TDO pin is tri-stated unless TAP states that shift out data are entered. Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port F is an input Port only. 2.3.9 Port G (PG4:PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
PAGE 8
3. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.
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ATmega128A 5.
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5.
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ATmega128A 5. Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $02 ($22) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 88 $01 ($21) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 88 $00 ($20) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 89 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2.
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6.
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ATmega128A 6.
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6. Instruction Set Summary (Continued) SES Set Signed Test Flag S←1 S CLS Clear Signed Test Flag S←0 S Description Operation Flags SEV Set Twos Complement Overflow.
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ATmega128A 7. Ordering Information 7.1 ATmega128A Speed (MHz) 16 Notes: Power Supply 2.7 - 5.5V Ordering Code(2) Package(1) ATmega128A-AU ATmega128A-AUR(3) ATmega128A-MU ATmega128A-MUR(3) 64A 64A 64M1 64M1 Operation Range Industrial (-40oC to 85oC) 1. The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
PAGE 16
8. Packaging Information 8.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
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ATmega128A 8.2 64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B K Option C b e BOTTOM VIEW Notes: Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 b 0.18 0.25 0.30 D 8.90 9.00 9.10 D2 5.20 5.40 5.60 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e NOTE 0.50 BSC L 0.35 0.40 0.
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9. Errata The revision letter in this section refers to the revision of the ATmega128A device. 9.1 ATmega128A Rev.
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ATmega128A NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation NOP ; no operation SEI ; set global interrupt enable 4. Stabilizing time needed when changing OSCCAL Register After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly. Problem Fix / Workaround The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata. 5.
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10. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 10.1 10.2 Rev. 8151H – 02/11 1. Editing update according to the Atmel new style guide. No more space betweeen the numbers and their units. 2. Updated the last page. Rev. 8151G – 07/10 1. 10.3 10.4 10.5 20 Updated the table note of Table 27-3 on page 324.
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10.6 Rev. 8151C – 05/09 1. 10.7 10.8 Updated “Errata” on page 375. ATmega128A Rev. U. Rev. 8151B – 03/09 1. Updated view of “Typical Characteristics” on page 337 view. 2. Editorial updates. Rev. 8151A– 08/08 1. Initial revision. (Based on the ATmega128/L datasheet 2467R-AVR-06/08) Changes done compared to the ATmega128/L datasheet 2467R-AVR-06/08: - Updated “Stack Pointer” on page 13 description. - “Power Management and Sleep Modes” on page 46 is reorganized.
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg.