Datasheet

90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Electrical Specification 66 April 2, 2013
7.3.2 DMA TIMING (MASTER MODE)
The DMA timing is as shown in Figure-18 and Table-17.
Figure-18 DMA Timing Diagram
Table-17 DMA Timing Specification
Symbol Description Min. Typical Max. Unit
t
PD
Output Delay 50 ns
SCLK
(CLK_IDLE=0)
SCLK
(CLK_IDLE=1)
SDI/SDO
CS
t
PD