Datasheet

90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Electrical Specification 65 April 2, 2013
7.3 INTERFACE TIMING
7.3.1 SPI INTERFACE TIMING (SLAVE MODE)
The SPI interface timing is as shown in Figure-17 and Table-16.
Figure-17 SPI Timing Diagram
Table-16 SPI Timing Specification
Symbol Description Min. Typical Max. Unit
t
CSH
Minimum CS High Level Time
2T
note 1
+10
ns
t
CSS
CS Setup Time 2T+10 ns
t
CSD
CS Hold Time 3T+10 ns
t
CLD
Clock Disable Time 1T ns
t
CYC
SCLK cycle 7T+10 ns
t
CLH
Clock High Level Time 5T+10 ns
t
CLL
Clock Low Level Time 2T+10 ns
t
DIS
Data Setup Time 2T+10 ns
t
DIH
Data Hold Time 1T+10 ns
t
DW
Minimum Data Width 3T+10 ns
t
PD
Output Delay 2T+20 ns
t
DF
Output Disable Time 2T+20 ns
Note:
1. T means system clock cycle. T=1/f
sys_clk
CS
SCLK
SDI
SDO
t
CSH
t
CSS
High Impedance High Impedance
t
CSD
t
CLH
t
CLL
t
DIS
t
DIH
t
PD
t
DF
Valid Input
Valid Output
t
CLD
t
DW
t
CYC