Datasheet
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Register 53 April 2, 2013
MMode1
PGA Gain Configuration
Address: 34H
Type: Read/Write
Default Value: 0000H
Bit Name Description
15-14 DPGA_GAIN
Digital PGA gain for the 4 current channels. This gain is implemented at the end of decimation filter.
00: Gain = 1 (default)
01: Gain = 2
10: Gain = 4
11: Gain = 8
13-0 PGA_GAIN
PGA gain for all ADC channels.
Mapping:
[13:12]: V3
[11:10]: V2
[9:8]: V1
[7:6]: I4
[5:4]: I3
[3:2]: I2
[1:0]: I1
Encoding:
00: 1X (default)
01: 2X
10: 4X
11: N/A