Datasheet

90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Register 44 April 2, 2013
DMACtrl
DMA Mode Interface Control
6.2.4 LAST SPI DATA REGISTER
LastSPIData
Last Read/Write SPI Value
Address: 0EH
Type: Read/Write
Default Value: 7E44H
Bit Name Description
15:9 ADC_CH_SEL
These bits configure the data source of the ADC channel. Each bit enables the data dumping for one ADC channel as the follow-
ing diagram shows. Set a ‘1’ to a bit enables the dumping of the corresponding ADC channel samples.
Note: I1 to phase A and I3 to phase C mapping can be swapped by configuring the I1I3Swap bit (b13, MMode0).
8 PIN_DIR_SEL
This bit configures the direction of the SDI and SDO pins.
7:6 CH_BIT_WIDTH
These bits configure the bit width for each channel.
5CLK_IDLE
This bit configures the Idle state clock level.
0: Idle low (default)
1: Idle High
4CLK_DRV
This bit configures which edge to drive data out.
0: Second edge drives data out. (default)
1: First edge drives data out.
3:0 CLK_DIV Divide ratio to generate SCLK frequency from SYS_CLK. Default value is ‘100’.
Address: 0FH
Type: Read
Default Value: 0000H
Bit Name Description
15:0
LastSPIData15 -
LastSPIData0
This register is a special register which logs data of the previous SPI Read or Write access especially for Read/Clear registers.
This register is useful when the user wants to check the integrity of the last SPI access.
b15 b14 b13 b12 b11 b10 b9
I4 V1I1 V2I2 V3I3
PIN_DIR_SEL
Master Mode
(DMA_Ctrl=1)
0
SDI→MOSI
SDO←MISO
1
SDI←MISO
SDO→MOSI
Code Channel Bit Width
00
32 bits
01
24 bits (default)
10
16 bits
11
reserved