Datasheet

90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Register 37 April 2, 2013
6.2.2 IRQ AND WARNOUT SIGNAL GENERATION
Status bits in the SysStatus0 register generate an interrupt and get
the IRQ0 pin to be asserted if the corresponding enable bits are set in
the FuncEn0 register.
Status bits in the SysStatus1 register generate an interrupt and get
the IRQ1 pin to be asserted, if the corresponding enable bits are set in
the FuncEn1 register.
Some of the status signals can also assert the WarnOut pin.
The following diagram illustrates how the status bits, enable bits and
IRQ/ WarnOut pins work together.
Figure-14 IRQ and WarnOut Generation
Status 1
Status 2
Status n
Enable 2
Enable n
Register bits in
SysStatus0/1
Register bits in
FuncEn0/1
IRQ0/1
WarnOut
event capture
event capture
EN
Status without
enable
Status with enable
Read clearRead clear
Read clearRead clear
Read clearRead clear