Datasheet

90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
SPI / DMA Interface 31 April 2, 2013
Figure-19 Sample Bit Sequence Example
4.3.2 CONTROL SEQUENCE FOR EXTERNAL DEVICE
To start and stop the DMA dump sequence, the external device fol-
lows the rules described below:
• Start of the dump process:
a) The external device configures the DMACtrl register.
b) The external device switches to SPI slave mode. Note that the
parameters of clock idle state / driving edge, sample bit width and pin
direction of SPI_D0/SPI_D1 configured to 90E36A should match with
external device's settings.
c) The external device asserts the DMA_CTRL signal. The 90E36A
swaps I/O direction if necessary after it has detected that master has
asserted the DMA. The samples are dumped out with a delay of at most
1 sample period (125us).
• Stop of the dump process:
a) The external device de-asserts the DMA_CTRL signal. The 90E
36A stops the transaction after current (all selected) samples have been
successfully sent out.
b) The external device waits one sample period of 125us or detects
that the CS signal is pulled high, then switches the interface back to
master mode.
Samples
Samples on MOSI
CS
I1 I2 V3
b
23
b
16
b
15
b
8
b
7
b
0
0000
I1 sample N
8 pads
0000