Datasheet

90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC

SPI / DMA Interface 30 April 2, 2013

Figure-17 Clock Mode2 (CLK_DRV=1, CLK_IDLE=0) and Mode3 (CLK_DRV=1, CLK_IDLE=1)

For mode0 and mode1 (CLK_DRV = 0), the first edge of SCLK is

used by the slave to sample the data.

For mode2 and mode3 (CLK_DRV=1), the first edge of SCLK is used

by the master to drive out the data.

CS Deactivation for Rate Adaptation

Since the bit rate may be higher than the equivalent bit rate of the

samples (For example, for 24-bit non-frame mode, the equivalent bit-

rate is sample_rate*6*24bps). To compensate for that, the CS signal is

de-asserted to wait for the new samples and be asserted again once the

new sample arrives.

There are at least 2 SCLK clock periods for CS resume from de-

asserted state to assert state depending on the Clock Dividing Ratio and

ADC Channel Selection. During CS de-asserted state, the SCLK stays

in idle state as configured by the CLK_IDLE bit (b5, DMACtrl).

Data Frame Format and Sample Sequence in DMA Mode

The 90E36A sends the ADC samples (In 8K sample rate) continu-

ously in DMA mode.

The samples of all enabled ADC channels are sent out in interleaved

manner, with the sequence of I4, I1, V1, I2, V2, and I3, V3 (If any chan-

nel is disabled, remove it from the list while maintaining the sequence of

the other channels). Figure-18 shows an example of the sample

sequence when the ADC_CH_SEL[15:9] bits (b15~9, DMACtrl) are con-

figured to be ‘0101001’.

Figure-18 Sample Sequence Example

Bit Sequence

The samples sent over the interfaces are the processed data accord-

ing to the CH_BITWIDTH[7:6] bits (b7~6, DMACtrl). All the samples sent

are MSB first. Figure-19 shows an example of sample bit sequence for

32-bit sample bit width.

CLOCK Cycle #

SCLK

(CLK_IDLE=0)

SCLK

(CLK_IDLE=1)

SDI/SDO

1234 N-2 NN-1

Samples on

MOSI

I2 V3 I1 I2 V3

I1 I2 V3

Samples 1

T=125µs

Samples 2

Samples N