Datasheet

90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
SPI / DMA Interface 28 April 2, 2013
4.2 SLAVE MODE: SPI INTERFACE
The interface works in slave mode when the DMA_CTRL pin is low
as shown in Figure-12.
4.2.1 SPI SLAVE INTERFACE FORMAT
In the SPI mode, data on SDI is shifted into the chip on the rising
edge of SCLK while data on SDO is shifted out of the chip on the falling
edge of SCLK.
Refer to Figure-14 and Figure-15 below for the timing diagram.
Access type:
The first bit on SDI defines the access type as below:
Address:
Fixed 15-bit, following the access type bits. The lower 10-bit is
decoded as address; the higher 5 bits are ‘Don't Care’.
Read/Write data:
Fixed as 16 bits.
Read Sequence:
Figure-14 Read Sequence
Write Sequence:
Figure-15 Write Sequence
4.2.2 RELIABILITY ENHANCEMENT FEATURE
The SPI read/write transaction is CS-low defined. Each transaction
can only access one register.
Within each CS-low defined transaction:
Write: access occurs only when CS goes from low to high and there
are exactly 32 SCLK cycles received during CS low period.
Read: if SCLK>=16 (full address received), data is read out from
internal registers and gets to the SDO pin; and the LastSPIData register
is updated. The R/C registers can only be cleared after the LastSPIData
register is updated.
Instruction Description Instruction Format
Read read from registers 1
Write write to registers 0
CS
SCLK
SDI
SDO
101 2 3 4 5 6 7 8 9 111213141516171819202122
24
A3A6 A5 A4
Register Address
High Impedance
D15
Don't care
D0
16-bit data
23
D14 D13 D12 D11
D10 D9 D8
D7 D6
D5 D4
D3 D2 D1
25 26
A2 A1 A0
27 28 29 30 31 32
A8
XXXXX
A7
A9
CS
SCLK
SDI
SDO
10123456789 11121314151617181920212223
A3A7 A6 A5 A4
16-bit data
High Impedance
D0D7 D6 D5 D4 D3 D2 D1
Register Address
D15
24
D14 D13 D12 D11 D10
D9 D8
A0A1A2
25 26
27 28 29 30 31 32
A8
XXXXX A9