Poly-Phase High-Performance Wide-Span Energy Metering IC 90E36A Version 1.
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Table of Contents FEATURES .............................................................................................................................................................................. 7 APPLICATION ......................................................................................................................................................................... 7 GENERAL DESCRIPTION ........................................................................................................
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 5.2 PARTIAL MEASUREMENT MODE CALIBRATION ..................................................................................................................................... 28 6.1 6.2 REGISTER LIST ............................................................................................................................................................................................ 29 SPECIAL REGISTERS .................................
List of Tables Table-1 Table-2 Table-3 Table-4 Table-5 Table-6 Table-7 Table-8 Table-9 Table-10 Table-11 Table-12 Table-13 Table-14 Table-15 Table-16 Table-17 Table-18 Pin Description ............................................................................................................................................................................................. Power Mode Mapping ......................................................................................................................
List of Figures Figure-1 Figure-2 Figure-3 Figure-4 Figure-5 Figure-6 Figure-7 Figure-8 Figure-9 Figure-10 Figure-11 Figure-12 Figure-13 Figure-14 Figure-15 Figure-16 Figure-17 Figure-18 Figure-19 Figure-20 Figure-21 90E36A Block Diagram .................................................................................................................................................................................. 8 Pin Assignment (Top View) ..................................................................
Poly-Phase High-Performance 90E36A Wide-Span Energy Metering IC Preliminary Information* FEATURES • Fundamental (CF3, 0.2%) and harmonic (CF4, 1%) active energy with dedicated energy and power registers. • Total Harmonic Distortion (THD) and Discrete Fourier Transform (DFT) functions for 2 ~ 32 order harmonic component. THD and DFT results available in SPI accessible registers. Both voltage and current of all phases processed within the same time period.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC BLOCK DIAGRAM OSCI RESET PM1 PM0 Power On Reset Crystal Oscillator VDD18 Regulator Power Mode Configuration Energy Metering (Forward/Reverse Active/Reactive/CF Generator) Current Detector I1P / I1N I2P / I2N I3P / I3N ADC-I1 ADC-I2 ADC-I3 I4P / I4N ADC-IN V1P / V1N V2P / V2N V3P / V3N ADC-V1 ADC-V2 ADC-V3 Measure and Monitoring (V/I/rms / SAG / Phase / Frequency) DSP Signal Analyzer ADC Sample Capture / THD CF Out CF1 CF2 CF3
0E36A DGND NC NC DGND VDD18 VDD18 RESET SDI SDO SCLK CS 46 45 44 43 42 41 40 39 38 37 AGND 47 1 DVDD AVDD 48 PIN ASSIGNMENT 7 30 IRQ0 I3N 8 29 WarnOut I4P 9 28 CF4 I4N 10 27 CF3 Vref 11 26 CF2 AGND 12 25 CF1 ZX2 24 I3P 23 IRQ1 ZX1 31 22 6 ZX0 I2N 21 TEST OSCO 32 20 5 OSCI I2P 19 PM 0 DGND 33 18 4 V3N I1N 17 PM 1 V3P 34 16 3 V2N I1P 15 NC V2P 35 14 2 V1N DM A_CTRL 13 36 V1P 1 POLY-PHASE HIGH-PERFORMANCE WIDE-SP
90E36A 2 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PIN DESCRIPTION Table-1 Pin Description Name Pin No.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-1 Pin Description (Continued) Name Pin No.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3 FUNCTION DESCRIPTION - 3.1 POWER SUPPLY - - 3.3.1 The 90E36A works with single power rail 3.3V. An on-chip voltage regulator regulates the 1.8V voltage for the digital logic. Any reset pulse that is shorter than 2μs can not reset the 90E36A. The 90E36A has multiple power modes, in Idle and Detection modes the 1.8V power regulator is not turned on and the digital logic is not powered.
90E36A 3.4 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC METERING FUNCTION sheet. The internal energy resolution for accumulation and conversion is 0.01 CF. The accumulated energy is converted to pulse frequency on the CF pins and stored in the corresponding energy registers. The 90E36A provides energy accumulation registers with 0.1 or 0.01 CF resolution. 0.01CF / 0.1CF setting is defined by the 001LSB bit (b9, MMode0). 3.4.1 The 0.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC A/B/C Power Phase-A Phase-B Phase-C ENA ENB ENC Bi-directional Energy accumulator, roll over Bi-directional Energy positive/nega accumulator, roll over tive @ positive/negative @ 0.01CF 0.01CF (+)0.01 Forward CF energy (+)0.01 Forward accumulator CF energy (+)0.01 Forward energy (-)0.01 accumulator CF Backwardregister CF energy (-)0.01 accumulator Backward accumulator CF energy (-)0.
90E36A 3.4.2 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC The fundamental/harmonic energy is accumulated in the same way as active energy accumulation method described above. ENERGY REGISTERS The 90E36A meters non-decomposed total active, reactive and apparent energy, as well as decomposed active fundamental and harmonic energy. The registers are listed as below. 3.4.2.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Power Threshold |P|+|Q|> PPhaseTh? A/B/C Phase Active Power from DSP 0 Total Active Power 3 phases ABS > PStartTh? + 1 Phase Active Energy Metering 0 0 0 Power Threshold |P|+|Q|> QPhaseTh? Phase ReActive Power from DSP 0 Total ReActive Power 3 phases 0 1 Total ReActive Energy Metering ABS > QStartTh? + 1 1 0 Power Threshold |P|+|Q|> SPhaseTh? 0 0 Total Apparent Power 3 phases Phase Apparent Power from DSP Phase ReActiv
90E36A 3.5 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MEASUREMENT FUNCTION - Measured parameters can be divided to 7 types as follows: - Active/ Reactive/ Apparent Power - Fundamental/ Harmonic Power - RMS for Voltage and Current - Power Factor - Phase Angle - Frequency - Temperature Altogether there are 8 power registers. Refer to 6.6.2 Fundamental/ Harmonic Power and Voltage/ Current RMS Registers. 3.5.
90E36A 3.5.5 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Refer to 6.6.3 THD+N, Frequency, Angle and Temperature Registers. PHASE ANGLE Phase Angle measurement registers can be divided as below: - phase A / phase B / phase C - voltage / current 3.5.8 Voltage THD+N is defined as: Altogether there are 6 phase angle registers. Refer to 6.6.3 THD+N, Frequency, Angle and Temperature Registers.
90E36A 3.6 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC FOURIER ANALYSIS FUNCTION nd The registers can be divided as follows: - voltage and current for each phase - phase A / phase B / phase C - 32 frequency components (fundamental value, and harmonic ratios) - Total Harmonic Distortion (THD) nd The 90E36A offers a hardware DFT Engine for 2 to 32 order harmonic component, both V and I of each phase with the same time period. The harmonic analysis is implemented with a DFT engine.
90E36A 3.7 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC POWER MODE 3.7.1 NORMAL MODE (N MODE) In Normal mode, all function blocks are active except for current detector block. Refer to Figure-7. The 90E36A has four power modes. The power mode is solely defined by the PM1 and PM0 pins.
90E36A 3.7.2 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC The digital I/Os' supply is powered. IDLE MODE (I MODE) In I/O and analog interface, the input signals from digital core (which is not powered) will be set to known state as described in Table-3. The PM1 and PM0 pins which are controlled by external MCU are active and can configure the 90E36A to other modes. In Idle mode, all functions are shut off.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-3 Digital I/O and Power Pin States in Idle Mode Name I/O type Type ZX0 ZX1 ZX2 O LVTTL 0 CF1 CF2 CF3 CF4 O LVTTL 0 WarnOut O LVTTL 0 IRQ0 IRQ1 O LVTTL 0 DMA_CTRL I LVTTL I/O set in input mode. Input level shall be VDD33 or VSS. VDD18 I Power Regulated 1.
90E36A 3.7.3 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC The digital I/O state is the same as that in Idle state (except for IRQ0/ IRQ1 and PM1/PM0). DETECTION MODE (D MODE) In Detection mode, the current detector is active. The current detector compares whether any phase current exceeds the configured threshold using low-power comparators. The 90E36A has two comparators for detecting each phase’s positive and negative current. Each comparator’s threshold can be set individually.
90E36A 3.7.4 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC In this mode, the user needs to program the related registers (including PGA gain, channel gain, offset, etc.) to make the current RMS measurement accurate. Refer to 5.2 Partial Measurement mode Calibration. Please note that not all registers in this mode is accessible. Only the Partial Measurement related registers (14H~1DH) and some special registers (00H, 01H, 03H, 07H,0EH, 0FH) can be accessed.
90E36A 3.7.5 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC TRANSITION OF POWER MODES The above power modes are controlled by the PM0 and PM1 pins. In application, the PM0 and PM1 pins are connected to external MCU. The PM0 and PM1 pins have internal RC- filters. Normal Mode Generally, the 90E36A stays in Idle mode most of the time while outage. It enters Detection mode at a certain interval (for example 5s) as controlled by the MCU.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 3.8 EVENT DETECTION 3.8.4.2 3.8.1 ZERO-CROSSING DETECTION The neutral line computed current (calculated) RMS is checked with the threshold defined in the INWarnTh0 register. If the N Line current is greater than the threshold, the INOv0 bit (b14, SysStatus1) bit is set. IRQ1 is generated if the corresponding Enable bit the INOv0En bit (b14, FuncEn1) is set.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 4 SPI / DMA INTERFACE 4.1 INTERFACE DESCRIPTION Five pins are associated with the interface as below: SDI – Data pin, bi-directional. SDO – Data pin, bi-directional. SCLK – Bi-directional pin. It is a clock output pin in master mode and clock input pin in slave mode. • CS – Bi-directional chip select pin . It is an output pin in master mode and input pin in slave mode. • DMA_CTRL – Uni-directional input pin.
90E36A 4.2 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC SLAVE MODE: SPI INTERFACE The interface works in slave mode when the DMA_CTRL pin is low as shown in Figure-12. 4.2.1 Instruction Read Write SPI SLAVE INTERFACE FORMAT In the SPI mode, data on SDI is shifted into the chip on the rising edge of SCLK while data on SDO is shifted out of the chip on the falling edge of SCLK.
90E36A 4.3 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MASTER MODE: DMA Clock Dividing Ratio The interface is defined to connect with various DSP processors for ADC samples dumping. The SCLK frequency of SPI interface is defined by the CLK_DIV[3:0] bits (b3~0, DMACtrl) as the following equation: For DMA configure please refer to DMACtrl register definition in 6.2 Special Registers. f SCLK = The interface works in Master mode when the DMA_CTRL pin is pulled high by the external device.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 1 CLOCK Cycle # 2 3 4 N-2 N-1 N SCLK (CLK_IDLE=0) SCLK (CLK_IDLE=1) SDI/SDO CS Figure-17 Clock Mode2 (CLK_DRV=1, CLK_IDLE=0) and Mode3 (CLK_DRV=1, CLK_IDLE=1) For mode0 and mode1 (CLK_DRV = 0), the first edge of SCLK is used by the slave to sample the data. ADC Channel Selection. During CS de-asserted state, the SCLK stays in idle state as configured by the CLK_IDLE bit (b5, DMACtrl).
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC I1 Samples I2 V3 Samples on MOSI CS b23 b16 b15 b8 b7 b0 0 0 0 0 0 0 0 0 8 pads I1 sample N Figure-19 Sample Bit Sequence Example 4.3.2 c) The external device asserts the DMA_CTRL signal. The 90E36A swaps I/O direction if necessary after it has detected that master has asserted the DMA. The samples are dumped out with a delay of at most 1 sample period (125us).
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 5 CALIBRATION METHOD 5.1 NORMAL MODE OPERATION CALIBRATION Step-3: Metering calibration (per phase) - First calibrate the Power/ Energy offset. • U = Un, I = 0. • Read full 32 bits (or lower 16 bits) Active and Reactive Power • Calculate the compensation values • Write the calculated values to the offset registers respectively. - Then calibrate Energy gain at unity power factor: • PF=1.0, U = Un, I = In (Ib).
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6 REGISTER 6.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address Register Name Read/Write Type Functional Description Comment Page Configuration Registers 30H ConfigStart R/W Calibration Start Command P 51 31H PLconstH R/W High Word of PL_Constant P 51 32H PLconstL R/W Low Word of PL_Constant P 51 33H MMode0 R/W Metering method configuration P 52 P 53 34H MMode1 R/W PGA gain configuration 35H PStartTh R/W Active Startup Pow
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address Register Name Read/Write Type Functional Description Comment Page Measurement Calibration 60H AdjStart R/W Measurement Calibration Startup Command 61H UgainA R/W Phase A Voltage RMS Gain 62H IgainA R/W Phase A Current RMS Gain 63H UoffsetA R/W Phase A Voltage RMS Offset 64H IoffsetA R/W Phase A Current RMS Offset 65H UgainB R/W Phase B Voltage RMS Gain 66H Igain
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address Register Name Read/Write Type Functional Description Comment Page Fundamental / Harmonic Energy Register A0H APenergyTF R/C Total Forward Active Fundamental Energy A1H APenergyAF R/C Phase A Forward Active Fundamental Energy A2H APenergyBF R/C Phase B Forward Active Fundamental Energy A3H APenergyCF R/C Phase C Forward Active Fundamental Energy A4H ANenergyTF R/C Tota
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address Register Name Read/Write Type Functional Description Comment Page Power and Power Factor Registers B0H PmeanT R Total (all-phase-sum) Active Power B1H PmeanA R Phase A Active Power B2H PmeanB R Phase B Active Power B3H PmeanC R Phase C Active Power B4H QmeanT R Total (all-phase-sum) Reactive Power B5H QmeanA R Phase A Reactive Power B6H QmeanB R Phase B Reacti
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address Register Name Read/Write Type Functional Description Comment Page Fundamental / Harmonic Power and Voltage / Current RMS Registers D0H PmeanTF R Total active fundamental power D1H PmeanAF R phase A active fundamental power D2H PmeanBF R phase B active fundamental power D3H PmeanCF R phase C active fundamental power D4H PmeanTH R Total active harmonic power D5H Pmean
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-4 Register List (Continued) Register Address Register Name Read/Write Type Functional Description Comment Page THD+N, Frequency, Angle and Temperature Registers F1H THDNUA R phase A voltage THD+N F2H THDNUB R phase B voltage THD+N F3H THDNUC R phase C voltage THD+N F5H THDNIA R phase A current THD+N F6H THDNIB R phase B current THD+N F7H THDNIC R phase C current THD+N F8H Freq R Frequency F9H PAngleA
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.2 SPECIAL REGISTERS 6.2.1 SOFT RESET REGISTER SoftReset Software Reset Address: 00H Type: Write Default Value: 0000H Bit 15 - 0 Register Name Description Software reset register. The 90E36A resets only if 789AH is written to this register. The reset domain is the same as the RESET SoftReset[15:0] pin or Power On Reset. Reading this register always return 0.
90E36A 6.2.2 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Status bits in the SysStatus1 register generate an interrupt and get the IRQ1 pin to be asserted, if the corresponding enable bits are set in the FuncEn1 register. IRQ AND WARNOUT SIGNAL GENERATION Status bits in the SysStatus0 register generate an interrupt and get the IRQ0 pin to be asserted if the corresponding enable bits are set in the FuncEn0 register. Some of the status signals can also assert the WarnOut pin.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC SysStatus0 System Status 0 Address: 01H Type: Read/Clear Default Value: 0000H Bit 15 Name - Description Reserved. * This bit indicates CS0 (3BH) checksum status. 0: CS0 checksum correct (default) 1: CS0 checksum error. The WarnOut pin is asserted at the same time. 14 CS0Err 13 - 12 CS1Err 11 - 10 CS2Err 9 - 8 CS3Err This bit indicates CS3 (6FH) checksum status. 0: CS3 checksum correct (default) 1: CS3 checksum error.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC SysStatus1 System Status 1 Address: 02H Type: Read/Clear Default Value: 0000H Bit Name Description 15 INOv1 This bit indicates whether the N line current sampling value is greater than the threshold set by the INWarnTh1 register. 0: Not greater than the threshold (default) 1: Greater than the threshold. 14 INOv0 This bit indicates whether the calculated N line current is greater than the threshold set by the INWarnTh0 register.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC FuncEn0 Function Enable 0 Address: 03H Type: Read/Write Default Value: 0000H Bit 15-11 Name - 10 CS2ErrEn 9-8 - 7 URevWnEn This bit determines whether to enable the interrupt when the URevWn bit (b7, SysStatus0) is set. 0: disable (default) 1: enable 6 IRevWnEn This bit determines whether to enable the interrupt when the IRevWn bit (b6, SysStatus0) is set.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC FuncEn1 Function Enable 1 Address: 04H Type: Read/Write Default Value: 0000H Bit Name 15 INOv1En This bit determines whether to enable the interrupt when the INOv1 bit (b15, SysStatus1) is set. 0: disable (default) 1: enable 14 INOv0En This bit determines whether to enable the interrupt when the INOv0 bit (b14, SysStatus1) is set.
90E36A 6.2.3 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC SPECIAL CONFIGURATION REGISTERS ZXConfig Zero-Crossing Configuration Address: 07H Type: Read/Write Default Value: 0001H Bit Name 15:13 ZX2Src[2:0] 12:10 ZX1Src[2:0] 9:7 ZX0Src[2:0] 6:5 ZX2Con[1:0] 4:3 ZX1Con[1:0] 2:1 ZX0Con[1:0] 0 ZXdis Description These bits select the signal source for the ZX2, ZX1 or ZX0 pins.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC INWarnTh0 Neutral Current (Calculated) Warning Threshold Address: 0AH Type: Read/Write Default Value: FFFFH Bit 15:0 Name Description INWarnTh0 Neutral current (calculated) warning threshold. Threshold for calculated (Ia + Ib +Ic) N line rms current. Unsigned 16 bit, unit 1mA. If N line rms current is greater than the threshold, The INOv0 bit (b14, SysStatus1) will be asserted if enabled. Refer to 3.8.4.2 Computed N-Line.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC DMACtrl DMA Mode Interface Control Address: 0EH Type: Read/Write Default Value: 7E44H Bit Name Description These bits configure the data source of the ADC channel. Each bit enables the data dumping for one ADC channel as the following diagram shows. Set a ‘1’ to a bit enables the dumping of the corresponding ADC channel samples.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.3 LOW-POWER MODES REGISTERS 6.3.1 DETECTION MODE REGISTERS Current Detection register latching scheme is: When any of the 4 current detection registers (0x10 - 0x13) were programmed, all the 4 current detection registers (including the registers that not being programmed) will be automatically latched into the current detector's internal configuration latches at the same time.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC DetectTh1 Channel 1 Current Threshold in Detection Mode Address: 11H Type: Read/Write Default Value: 0000H Bit Name 15 - 14:8 CalCodeN 7 - 6:0 CalCodeP Description Reserved. Channel 1 current negative detector calculation code. Code mapping: 7'b000-0000, Vc=-4.28mV=-3.03mVrms (Vc is the threshold of low power computation) 7'b111-1111, Vc=12.91mV=9.14mVrms DAC typical resolution is [12.91-(-4.28)]/127=135.4μV=95.7μVrms Reserved.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC DetectTh3 Channel 3 Current Threshold in Detection Mode Address: 13H Type: Read/Write Default Value: 0000H Bit Name 15 - 14:8 CalCodeN 7 - 6:0 CalCodeP Description Reserved. Channel 3 current negative detector calculation code. Code mapping: 7'b000-0000, Vc=-4.28mV=-3.03mVrms (Vc is the threshold of low power computation) 7'b111-1111, Vc=12.91mV=9.14mVrms DAC typical resolution is [12.91-(-4.28)]/127=135.4μV=95.7μVrms Reserved.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PMPGA PGAgain Configuration in Partial Measurement mode Address: 17H Type: Read/Write Default Value: 0000H Bit Name Description 15-14 DPGA 13:0 PGAGain DPGA in Partial Measurement mode. PGAGain in Partial Measurement mode Refer to the MMode1 register for encoding and mapping.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PMConfig Measure Configuration in Partial Measurement mode Address: 1BH Type: Read/Write Default Value: 0000H Bit Name 15 - 14 ReMeasure 13 Description Reserved. This bit is ‘1’-write-only. Write ‘1’ to this bit will trigger another measurement cycle. This bit configures start of measurement whether starts from zero crossing point.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.4 CONFIGURATION AND CALIBRATION REGISTERS 6.4.1 START REGISTERS AND ASSOCIATED CHECKSUM OPERATION SCHEME The Start Registers (ConfigStart (30H), CalStart (40H), HarmStart (50H) and AdjStart (60H)) and associated registers / checksum have a special operation scheme to protect important configuration data, illustrated below in the diagram. Start registers have multiple valid settings for different operation modes.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-5 Configuration Registers Register Address Register Name Read/Write Type Functional Description Power-on Value and Comments 38H PPhaseTh R/W Startup power threshold (for |P|+|Q| of a phase) for 0000H any phase participating Active Energy Accumula- 16 bit unsigned integer, tion. Common for phase A/B/C. Unit: 0.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MMode0 Metering method configuration Address: 33H Type: Read/Write Default Value: 0087H Bit Name 15-14 - Description Reserved. 13 I1I3Swap This bit defines phase mapping for I1 and I3: 0: I1 maps to phase A, I3 maps to phase C (default) 1: I1 maps to phase C, I3 maps to phase A Note: I2 always maps to phase B. 12 Freq60Hz Current Grid operating line frequency.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC MMode1 PGA Gain Configuration Address: 34H Type: Read/Write Default Value: 0000H Bit 15-14 Name DPGA_GAIN Description Digital PGA gain for the 4 current channels. This gain is implemented at the end of decimation filter. 00: Gain = 1 (default) 01: Gain = 2 10: Gain = 4 11: Gain = 8 PGA gain for all ADC channels.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC CS0 Checksum 0 Address: 3BH Type: Read/Write Default Value: 421CH Bit Name Description This register should be written after the 31H-3AH registers are written. Suppose the high byte and the low byte of the 31H-3AH registers are shown in the below table.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-6 Calibration Registers Register Address Register Name Read/Write Type Functional Description Power-on Value 4AH PhiB R/W Phase B calibration phase angle 0000H 4BH GainC R/W Phase C Active/Reactive Energy calibration gain 0000H 4CH PhiC R/W Phase C calibration phase angle 0000H 4DH * R/W Checksum 1 0000H CS1 Note: The calculation of the CS1 register is similar as the CS0 register by calculating the 41H-4CH regi
90E36A 6.4.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 6.5 ENERGY REGISTER 6.5.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC EnStatus0 Metering Status 0 Address: 95H Type: Read Default Value: F000H Bit Name 15 TQNoload all-phase-sum reactive power no-load condition detected. 14 TPNoload all-phase-sum active power no-load condition detected. 13 TASNoload all-phase-sum apparent power no-load condition detected. 12 TVSNoload all-phase-sum vectored sum apparent active power no-load condition detected.
90E36A 6.5.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-11 Power and Power Factor Register Register Address Register Name Read/Write Type Functional Description C1H PmeanALSB R Lower word of Phase A Active Power C2H PmeanBLSB R Lower word of Phase B Active Power C3H PmeanCLSB R Lower word of Phase C Active Power C4H QmeanTLSB R Lower word of Total (all-phase-sum) Reactive Power C5H QmeanALSB R Lower word of Phase A Reactive Power C6H QmeanBLSB R Lower word of Phase
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Register Address Read/Write Type Register Name Functional Description Comment E1H PmeanAFLSB R Lower word of phase A active fundamental Power E2H PmeanBFLSB R Lower word of phase B active fundamental Power E3H PmeanCFLSB R Lower word of phase C active fundamental Power E4H PmeanTHLSB R Lower word of Total active harmonic Power E5H PmeanAHLSB R Lower word of phase A active harmonic Power E6H PmeanBHLSB R Lower word
90E36A 6.7 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC HARMONIC FOURIER ANALYSIS REGISTERS Table-14 Harmonic Fourier Analysis Results Registers Register Address Register Name Read/Write Type 100H AI_HR2 R phase A, Current, Harmonic Ratio for 2-th order component 101H AI_HR3 R phase A, Current, Harmonic Ratio for 3-th order component 102H AI_HR4 R phase A, Current, Harmonic Ratio for 4-th order component … Functional Description Harmonic Ratio (%) = Register Value / 163.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Table-14 Harmonic Fourier Analysis Results Registers Register Address Register Name Read/Write Type Functional Description 180H BV_HR2 R phase B, Voltage, Harmonic Ratio for 2-th order component 181H BV_HR3 R phase B, Voltage, Harmonic Ratio for 3-th order component 182H BV_HR4 R phase B, Voltage, Harmonic Ratio for 4-th order component … BV_HR32 R phase B, Voltage, Harmonic Ratio for 32-th order component 19FH BV_THD R
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7 ELECTRICAL SPECIFICATION 7.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Parameter Min Typ Max DC Characteristics VDD 0.8 ±1 0.4 Digital Input High Level (all digital pins except OSCI) 2.4 Digital Input Low Level (all digital pins except OSCI) Digital Input Leakage Current Digital Output Low Level (CF1, CF2, CF3, CF4) Digital Output Low Level (IRQ0, IRQ1, WarnOut, ZX0, ZX1, ZX2, SDO) Digital Output High Level (CF1, CF2, CF3, CF4) 2.8 Digital Output High Level (IRQ0, IRQ1, WarnOut, ZX0, ZX1, ZX2, SDO) 2.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.2 METERING/ MEASUREMENT ACCURACY 7.2.1 METERING ACCURACY γ= Metering accuracy or energy accuracy is calculated with relative error: E mea − E real × 100% E real Where Emea is the energy measured by the meter, Ereal is the actual energy measured by a high accurate normative meter.
90E36A 7.2.2 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC Where Umea means the measured data of one measurement parameter, and Ureal means the real/actual data of the parameter, MEASUREMENT ACCURACY The measurements are all calculated with fiducial error except for frequency and THD. UFV means the fiducial value of this measurement parameter, which can be defined as Table-15.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC 7.3 INTERFACE TIMING 7.3.1 SPI INTERFACE TIMING (SLAVE MODE) The SPI interface timing is as shown in Figure-17 and Table-16.
90E36A 7.3.2 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC DMA TIMING (MASTER MODE) The DMA timing is as shown in Figure-18 and Table-17. SCLK (CLK_IDLE=0) SCLK (CLK_IDLE=1) SDI/SDO tPD CS Figure-18 DMA Timing Diagram Table-17 DMA Timing Specification Symbol tPD Electrical Specification Description Output Delay Min. 66 Typical Max.
90E36A 7.4 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC POWER ON RESET TIMING In most case, the power of 90E36A and MCU are both derived from 220V power lines. To make sure 90E36A is reset and can work properly, MCU must force 90E36A into idle mode firstly and then into normal mode. In this operation, RESET is held to high in idle mode and deasserted by delay T1 after idle-normal transition. Refer to Figure-19.
90E36A 7.5 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC ZERO-CROSSING TIMING V TZX ZX (Positive zero-crossing) TD ZX (Negative zero-crossing) ZX (All zero-crossing) Figure-21 Zero-Crossing Timing Diagram (per phase) Table-19 Zero-Crossing Specification Symbol TZX TD Description Min High Level Width Delay Time Electrical Specification 68 Typ 5 0.2 Max 0.
90E36A 7.
90E36A 7.7 POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC ABSOLUTE MAXIMUM RATING Parameter Relative Voltage Between AVDD and AGND Relative Voltage Between DVDD and DGND Analog Input Voltage (I1P, I1N, I2P, I2N, I3P, I3N, I4P, I4N, V1P, V1N, V2P, V2N, V3P, V3N) Digital Input Voltage Operating Temperature Range Maximum Junction Temperature Package Type TQFP48 Electrical Specification Maximum Limit -0.3V~3.7V -0.3V~3.7V -0.6V~AVDD -0.3V~3.6V -40~85 °C 150 °C Thermal Resistance θJA 58.
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC PACKAGE DIMENSIONS 70 April 2, 2013
90E36A POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC ORDERING INFORMATION XXXXX Device Type XXX Package X Temperature Range DATASHEET DOCUMENT HISTORY 71 I Industry (-40 ℃ to +85 ℃) ERG TQFP48 90E36A Poly-Phase High-Performance Wide-Span Energy Metering IC
