Datasheet

List of Figures 6 April 2, 2013
Figure-1 90E32AS Block Diagram ............................................................................................................................................................................... 8
Figure-2 Pin Assignment (Top View) ............................................................................................................................................................................ 9
Figure-3 Channel to Phase Mapping .......................................................................................................................................................................... 13
Figure-4 Energy Accumulation Diagram .................................................................................................................................................................... 15
Figure-5 CFx Pulse Output Regulation ...................................................................................................................................................................... 16
Figure-6 Active Power Startup/Noload Processing .................................................................................................................................................... 17
Figure-7 Fundamental Active Power Startup/Noload Processing .............................................................................................................................. 17
Figure-8 Harmonic Active Power Startup/Noload Processing .................................................................................................................................... 18
Figure-9 Power Quality Monitor in Datapath .............................................................................................................................................................. 21
Figure-10 Block Diagram in Normal Mode ................................................................................................................................................................... 23
Figure-11 Block Diagram in Idle Mode ........................................................................................................................................................................ 24
Figure-12 Block Diagram in Detection Mode ............................................................................................................................................................... 26
Figure-13 Block Diagram in Partial Measurement mode ............................................................................................................................................. 27
Figure-14 Power Mode Transition ............................................................................................................................................................................... 28
Figure-15 Segment Gain Compensation ..................................................................................................................................................................... 30
Figure-16 Slave Mode ................................................................................................................................................................................................. 31
Figure-17 Read Sequence ........................................................................................................................................................................................... 32
Figure-18 Write Sequence ........................................................................................................................................................................................... 32
Figure-19 CRC Checking Diagram .............................................................................................................................................................................. 40
Figure-20 IRQ and WarnOut Generation ..................................................................................................................................................................... 41
Figure-21 Current Detection Register Latching Scheme ............................................................................................................................................. 48
Figure-22 SPI Timing Diagram .................................................................................................................................................................................... 75
Figure-23 Power On Reset Timing (90E32AS and MCU are Powered on Simultaneously) ........................................................................................ 76
Figure-24 Power On Reset Timing in Normal & Partial Measurement Mode .............................................................................................................. 76
Figure-25 Zero-Crossing Timing Diagram (per phase) ................................................................................................................................................ 77
Figure-26 Voltage Sag and Phase Loss Timing Diagram ............................................................................................................................................ 78
List of Figures