Datasheet

90E32AS ENHANCED POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Register 58 April 2, 2013
PoffsetA
Phase A Active Power offset
QoffsetA
Phase A Reactive Power offset
GainA
Phase A Active/Reactive Energy Calibration Gain
PhiA
Phase A Calibration Phase Angle
5.4.3 FUNDAMENTAL/HARMONIC ENERGY CALIBRATION REGISTERS
Address: 41H
Type: Read/Write
Default Value: 0000H
Bit Name Description
15-0 offset Phase A active power offset, signed with complement format.
Address: 42H
Type: Read/Write
Default Value: 0000H
Bit Name Description
15-0 offset Phase A reactive power offset, signed with complement format.
Address: 47H
Type: Read/Write
Default Value: 0000H
Bit Name Description
15-0 Gain Phase A energy gain, signed with complement format.
Address: 48H
Type: Read/Write
Default Value: 0000H
Bit Name Description
15 DelayV
0: Delay Cycles are applied to current channel. (default)
1: Delay Cycles are applied to voltage channel.
14:8 - Reserved.
7:0 DelayCycles
Number of delay cycles calculated in phase compensation.
Unit is 2.048MHz cycle. It is an unsigned 8 bit integer.
Table-8 Fundamental/Harmonic Energy Calibration Registers
Register
Address Register Name
Read/Write
Type Functional Description Power-on Value
51H PoffsetAF R/W Phase A Fundamental Active Power offset 0000H
52H PoffsetBF R/W Phase B Fundamental Active Power offset 0000H
53H PoffsetCF R/W Phase C Fundamental Active Power offset 0000H
54H PGainAF R/W Phase A Fundamental Calibration Gain 0000H
55H PGainBF R/W Phase B Fundamental Calibration Gain 0000H
56H PGainCF R/W Phase C Fundamental Calibration Gain 0000H