Datasheet

90E32AS ENHANCED POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Register 57 April 2, 2013
MMode1
PGA Gain Configuration
5.4.2 ENERGY CALIBRATION REGISTERS
Address: 34H
Type: Read/Write
Default Value: 0000H
Bit Name Description
15-14 - Reserved.
13-0 PGA_GAIN
PGA gain for all ADC channels.
Mapping:
[13:12]: V3
[11:10]: V2
[9:8]: V1
[7:6]: -
[5:4]: I3
[3:2]: I2
[1:0]: I1
Encoding:
00: 1X (default)
01: 2X
10: 4X
11: N/A
Table-7 Calibration Registers
Register
Address Register Name
Read/Write
Type Functional Description Power-on Value
Calibration Registers
41H PoffsetA R/W Phase A Active Power Offset 0000H
42H QoffsetA R/W Phase A Reactive Power Offset 0000H
43H PoffsetB R/W Phase B Active Power Offset 0000H
44H QoffsetB R/W Phase B Reactive Power Offset 0000H
45H PoffsetC R/W Phase C Active Power Offset 0000H
46H QoffsetC R/W Phase C Reactive Power Offset 0000H
47H GainA R/W
Phase A Active/reactive Energy Calibration
Gain
0000H
48H PhiA R/W Phase A Calibration Phase Angle 0000H
49H GainB R/W
Phase B Active/reactive Energy Calibration
Gain
0000H
4AH PhiB R/W Phase B Calibration Phase Angle 0000H
4BH GainC R/W
Phase C Active/reactive Energy Calibration
Gain
0000H
4CH PhiC R/W Phase C Calibration Phase Angle 0000H