Datasheet

90E32AS ENHANCED POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Register 51 April 2, 2013
UDCoffsetC
Voltage DC offset for Channel C
UGainTAB
Voltage Gain Temperature Compensation for Phase A/B
UGainTC
Voltage Gain Temperature Compensation for Phase C
PhiFreqComp
Phase Compensation for Frequency
LOGIrms0
Current (Log Irms0) Configuration for Segment Compensation
Address: 19H
Type: Read/Write
Default Value: 0000H
Bit Name Description
15:0 UDCoffsetC Phase C voltage DC offset in decimator, signed with complement format.
Address: 1AH
Type: Read/Write
Default Value: 0000H
Bit Name Description
15:8 UGainTB Voltage gain temperature compensation for phase B.
7:0 UGainTA Voltage gain temperature compensation for phase A.
Address:1BH
Type: Read/Write
Default Value: 0000H
Bit Name Description
15:8 - Reserved.
7:0 UGainTC Voltage gain temperature compensation for phase C.
Address: 1CH
Type: Read/Write
Default Value: 0000H
Bit Name Description
15:8 - Reserved.
7:0 PhiF Phase compensation for frequency.
Address: 20H
Type: Read/Write
Default Value: 0000H
Bit Name Description
15:8 - Reserved.
7:0 LogIrms0 = log2(Irms0), Irms0 is the nominal RMS current at calibration.