Datasheet

90E32AS ENHANCED POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Function Description 24 April 2, 2013
3.8.2 IDLE MODE (I MODE)
In Idle mode, all functions are shut off.
The analog blocks' power supply is powered but circuits are set into
power-down mode, i.e, power supply applied but all current paths are
shut off. There is very low current since only very low device leakage
could exist in this mode.
The digital I/Os' supply is powered.
In I/O and analog interface, the input signals from digital core (which
is not powered) will be set to known state as described in Table-3. The
PM1 and PM0 pins which are controlled by external MCU are active and
can configure the 90E32AS to other modes.
Figure-11 Block Diagram in Idle Mode
Please note that since the digital I/O is not shut off, the I/O circuit is
active in the Idle mode. The application shall make sure that valid logic
levels are applied to the I/O.
Table-3 lists digital I/O and power pins’ states in Idle mode. It lists the
requirements for inputs and the output level for output.
VDD18 Regulator
Temperature Sensor
Current Detector
ADC-V1
ADC-V2
ADC-V3
ADC-I1
ADC-I2
ADC-I3
SPI Interface
DSP
Energy Metering
(Forward/Reverse
Active/Reactive/CF Generator)
Measure and Monitoring
(V/I/rms / SAG / Phase /
Frequency)
Control Logic
Zero
Crossing
CF Out
Power On Reset
Crystal Oscillator
On-chip
Reference Voltage
Vref
I1P / I1N
V1P / V1N
CS
SCLK
SDO
SDI
OSCI OSCO
RESET
CF1
ZX0
I2P / I2N
I3P / I3N
V2P / V2N
V3P / V3N
CF2
CF3
CF4
ZX1
ZX2
Power Mode
Configuration
PM1
PM0
IRQ
WarnOut
IRQ0
IRQ1
Warn
Out
Flexible Piece-wise Non-linear
Compensation
Disabled
Table-3 Digital I/O and Power Pin States in Idle Mode
Name I/O type Type Pin State in Idle Mode
Reset I LVTTL Input level shall be VDD33.
CS ILVTTL
I/O set in input mode.
Input level shall be VDD33 or VSS.
SCLK I LVTTL
I/O set in input mode.
Input level shall be VDD33 or VSS.
SDO O LVTTL
I/O set in input mode.
Input level shall be VDD33 or VSS.
SDI I LVTTL
I/O set in input mode.
Input level shall be VDD33 or VSS.
PM1
PM0
ILVTTL
As defined in Table-2.
OSCI
OSCO
I
O
OSC
Oscillator powered down.
OSCO stays at fixed (low) level.