Datasheet

90E32AS ENHANCED POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Function Description 22 April 2, 2013
3.7.2.1 Sag Detection
Usually in the application the Sag threshold is set to be 78% of the
reference voltage. The 90E32AS generates Sag event when there are
less than three 8KHz samples (absolute value) greater than the sag
threshold in one detecting period. Refer to 6.6 Voltage Sag and Phase
Loss Timing. The detecting period length can be configured by the
Sag_Period bits (b7~0, SagPeakDetCfg).
Sag status is asserted when there is no voltage instantaneous sam-
ple's absolute value goes beyond the Sag threshold in any phase. Sag
status is cleared when there are three samples detected with absolute
value above the Sag threshold.
For the computation of Sag threshold register value, refer to AN-644.
The Sag event is captured by the SagPhaseIntST bits (b14-12, E
MMIntState1). If the corresponding IRQ enable bits the SagPhaseIntEN
bits (b14-12, EMMIntEn1) is set, IRQ can be generated. Refer to Figure-
26.
3.7.2.2 Phase Loss Detection
The phase loss detection detects if there is one or more phases’ volt-
age is less than the phase-loss threshold voltage.
The processing and handling is similar to sag detection, only the
threshold is different. The threshold computation flow is also similar. The
typical threshold setting could be 10% Un or less.
If any phase line is detected as in phase-loss mode, that phase’s
zero-crossing detection function (both voltage and current) is disabled.
3.7.2.3 Over Voltage (OV) Detection
When any phase's absolute voltage sample instantaneous value
goes beyond the over voltage threshold, the Over Voltage status is
asserted. The status is de-asserted when the voltage sample instanta-
neous value go back below the over voltage threshold.
Change of the Over Voltage status can generate interrupt and
flagged in the EMMState0 and EMMIntState0 registers.
3.7.2.4 Over Current (OI) Detection
When any phase's absolute current sample instantaneous value go
beyond the over current threshold, the Over Current status is asserted.
The status is de-asserted when the current sample instantaneous value
go back below the over current threshold.
Change of the Over Current status can generate interrupt and
flagged in the EMMState0 and EMMIntState0 registers.
3.7.3 FREQUENCY MONITORING RELATED STATUS AND E
VENTS
The measured frequency is compared with two thresholds configured
in the the FreqLoTh register and the FreqHiTh register.
If the measured frequency goes beyond the range defined by the two
thresholds, the
FreqLoST bit (b11, EMMState1) and FreqHiST bit (b15, E
MMState1) will be asserted.
The interrupt status will be updated as well; and if enabled, interrupt
signal can be asserted.
3.7.4 ZERO-CROSSING DETECTION
Zero-crossing detector detects the zero-crossing point of the funda-
mental component of voltage and current for each of the 3 phases.
Refer to 6.5 Zero-Crossing Timing.
Zero-crossing signal can be independently configured and output.
Refer to the definition of the ZXConfig register.
3.7.5 NEUTRAL LINE OVERCURRENT DETECTION
The neutral line rms current (calculated) I
NC
is checked with the
threshold defined in the InWarnTh register. If the N Line current is
greater than the threshold, the INOv0ST bit (b7, EMMState0) is set.
IRQ0 is generated if the INOv0IntEN bit (b7, EMMIntEn0) is set.
3.7.6 PHASE SEQUENCE ERROR DETECTION
The phase sequence is detected in two cases: 3P4W and 3P3W,
which is defined by the 3P3W bit (b8, MMode0).
3P4W case:
Correct sequence: Voltage/current zero-crossing sequence: phase-
A, phase-B and phase-C.
3P3W case:
Correct sequence: Voltage/current zero-crossing between phase-A
and phase-C is greater than 180 degree.
If the above mentioned criteria are violated, it is assumed as a phase
sequence error, the URevWnST bit (b9, EMMState0) or the IRevWnST
bit (b9, EMMState0) will be set.