Datasheet
90E32AS ENHANCED POLY-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Pin Description 11 April 2, 2013
OSCI 20 I OSC
OSCI: External Crystal Input
OSCO: External Crystal Output
A 16.384 MHz crystal is connected between OSCI and OSCO. There are two on-chip capac-
itors, therefore no need of external capacitors.
OSCO 21 O OSC
ZX0
ZX1
ZX2
22
23
24
O LVTTL
ZX2/ZX1/ZX0:Zero-Crossing Output
These pins are asserted when voltage or current crosses zero. Zero-crossing mode can be
configured by the ZXConfig register (07H).
CF1 25 O LVTTL
CF1: (all-phase-sum total) Active Energy Pulse Output
CF2 26 O LVTTL
CF2: (all-phase-sum total) Reactive/ Apparent Energy Pulse Output
The output of this pin is determined by the CF2varh bit (b7, MMode0).
CF3 27 O LVTTL
CF3: (all-phase-sum total) Active Fundamental Energy Pulse Output
CF4 28 O LVTTL
CF4: (all-phase-sum total) Active Harmonic Energy Pulse Output
WarnOut 29 O LVTTL
WarnOut: Fatal Error Warning
This pin is asserted high when there is metering related parameter checksum error. Other-
wise this pin stays low. Refer to 5.2.2 IRQ and WarnOut Signal Generation.
IRQ0 30 O LVTTL
IRQ0: Interrupt Output 0
This pin is asserted when one or more events in the EMMIntState0 register (1CCH) occur. It
is deasserted when there is no bit set in the EMMIntState0 register (1CCH).
In Detection mode, the IRQ0 is used to indicate the output of current detector. The IRQ0
state is cleared when entering or exiting Detection mode.
IRQ1 31 O LVTTL
IRQ1: Interrupt Output 1
This pin is asserted when one or more events in the EMMIntState1 register (1D0H) occur. It
is deasserted when there is no bit set in the EMMIntState1 register (1D0H).
In Detection mode, the IRQ1 is used to indicate the output of current detector. The IRQ1
state is cleared when entering or exiting Detection mode.
PM0
PM1
33
34
I
2
LVTTL
PM1/0: Power Mode Configuration
These two pins define the power mode of 90E32AS. Refer to Ta bl e- 2.
CS 37
I
2
LVTTL
CS: Chip Select (Active Low)
In SPI mode, this pin must be driven from high to low for each read/ write operation, and
maintain low for the entire operation.
SCLK 38
I
2
LVTTL
SCLK: Serial Clock
This pin is used as the clock for the SPI interface. Refer to 4 SPI Interface.
SDO 39 O LVTTL
SDO: Serial Data Output
This pin is used as the data output for the SPI mode. Refer to 4 SPI Interface.
SDI 40
I
2
LVTTL
SDI: Serial Data Input
This pin is used as the data input for the SPI mode. Refer to 4 SPI Interface.
TEST 32 I LVTTL
This pin should be always connected to DGND in system application.
IC 9, 10, 36 LVTTL
These pins should be always connected to DGND in system application.
NC 35, 45, 46
NC: These pins should be left open.
Note 1: The channel mapping is only valid in Normal mode and Patial Measurement mode.
Note 2: All the digital input pins except OSCI are 5 V compatible.
Table-1 Pin Description (Continued)
Name Pin No. I/O Type Description