Datasheet
743
AT32UC3A
36.4 I/O Lines Description
36.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
36.5.1 I/O Lines
The JTAG interface pins are multiplexed with IO lines. When the JTAG is used the associated
pins must be enabled. To enable the JTAG pins TCK must be zero while RESET_N has a zero
to one transition. To disable the JTAG pins TCK must be one while RESET_N has a zero to one
transition.
While using the JTAG lines all normal peripheral activity on these lines are disabled. The user
must make sure that no external peripheral is blocking the JTAG lines while debugging.
36.6 Functional description
36.6.1 JTAG interface
The JTAG interface is accessed through the dedicated JTAG pins shown in Table 36-1 on page
743. The TMS control line navigates the TAP controller, as shown in Figure 36-2 on page 744.
The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data
is scanned into the selected instruction or data register on TDI, and out of the register on TDO,
in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and out first. TDO is high-
Z in other states than Shift-IR and Shift-DR.
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for 5 TCK clock periods. This sequence should always be applied
at the start of a JTAG session to bring the TAP Controller into a defined state before applying
JTAG commands. Applying a 0 on TMS for 1 TCK period brings the TAP Controller to the Run-
Test/Idle state, which is the starting point for JTAG operations.
The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions
defined by the JTAG standard are supported, as described in Section 36.8, as well as a number
of AVR32-specific private JTAG instructions described in Section 36.9. Each instruction selects
a specific data register for the Shift-DR path, as described for each instruction.
Table 36-1. I/O Lines Description
Name Description Type
TCK Test Clock Input. Fully asynchronous to system clock frequency. Input
TMS Test Mode Select, sampled on rising TCK Input
TDI Test Data In, sampled on rising TCK. Input
TDO Test Data Out, driven on falling TCK. Output
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