Datasheet

707
AT32UC3A
33.7 User Interface
Table 33-2. ADC Register Mapping
Offset Register Name Access Reset State
0x00 Control Register CR Write-only –
0x04 Mode Register MR Read/Write 0x00000000
0x10 Channel Enable Register CHER Write-only –
0x14 Channel Disable Register CHDR Write-only –
0x18 Channel Status Register CHSR Read-only 0x00000000
0x1C Status Register SR Read-only 0x000C0000
0x20 Last Converted Data Register LCDR Read-only 0x00000000
0x24 Interrupt Enable Register IER Write-only –
0x28 Interrupt Disable Register IDR Write-only –
0x2C Interrupt Mask Register IMR Read-only 0x00000000
0x30 Channel Data Register 0 CDR0 Read-only 0x00000000
... ...(if implemented) ... ... ...
0x4C
Channel Data Register 7(if implemented) CDR7 Read-only 0x00000000
0xFC Version Register VERSION Read-only –
32058K
AVR32-01/12