Datasheet

AT32UC3A

13.6.3 Clock Mask

Name: CPU/HSB/PBA/PBBMASK

Access Type: Read/Write

• MASK: Clock Mask

If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current

power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is

shown in Table 13-5.

31 30 29 28 27 26 25 24

MASK[31:24]

23 22 21 20 19 18 17 16

MASK[23:16]

15 14 13 12 11 10 9 8

MASK[15:8]

7 6 5 4 3 2 1 0

MASK[7:0]

Table 13-5. Maskable module clocks in AT32UC3A.

Bit CPUMASK HSBMASK PBAMASK PBBMASK

0 - FLASHC INTC HMATRIX

1 OCD PBA bridge GPIO USBB

2 - PBB bridge PDCA FLASHC

3 - USBB PM/RTC/EIC MACB

4 - MACB ADC SMC

5 - PDCA SPI0 SDRAMC

6 - EBI SPI1 -

7 - - TWI -

8 - - USART0 -

9 - - USART1 -

10 - - USART2 -

11 - - USART3 -

12 - - PWM -

13 - - SSC -

32058K

AVR32-01/12