Datasheet

684
AT32UC3A
32.7 Pulse Width Modulation (PWM) Controller User Interface
32.7.1 Register Mapping
Table 32-2. PWM Controller Registers
Offset Register Name Access
Peripheral
Reset Value
0x00 PWM Mode Register MR Read/Write 0
0x04 PWM Enable Register ENA Write-only -
0x08 PWM Disable Register DIS Write-only -
0x0C PWM Status Register SR Read-only 0
0x10 PWM Interrupt Enable Register IER Write-only -
0x14 PWM Interrupt Disable Register IDR Write-only -
0x18 PWM Interrupt Mask Register IMR Read-only 0
0x1C PWM Interrupt Status Register ISR Read-only 0
0x4C - 0xF8 Reserved – – –
0x4C - 0xFC Reserved – – –
0x100 - 0x1FC Reserved
0x200 Channel 0 Mode Register CMR0 Read/Write 0x0
0x204 Channel 0 Duty Cycle Register CDTY0 Read/Write 0x0
0x208 Channel 0 Period Register CPRD0 Read/Write 0x0
0x20C Channel 0 Counter Register CCNT0 Read-only 0x0
0x210 Channel 0 Update Register CUPD0 Write-only -
... Reserved
0x220 Channel 1 Mode Register CMR1 Read/Write 0x0
0x224 Channel 1 Duty Cycle Register CDTY1 Read/Write 0x0
0x228 Channel 1 Period Register CPRD1 Read/Write 0x0
0x22C Channel 1 Counter Register CCNT1 Read-only 0x0
0x230 Channel 1 Update Register CUPD1 Write-only -
... ... ... ... ...
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AVR32-01/12