Datasheet

654
AT32UC3A
31.7 Timer Counter (TC) User Interface
BCR (Block Control Register) and BMR (Block Mode Register) control the whole TC block. TC
channels are controlled by the registers listed in Table 31-4. The offset of each of the channel
registers in Table 31-4 is in relation to the offset of the corresponding channel as mentioned in
Table 31-4.
Notes: 1. Read-only if WAVE = 0
Table 31-3. TC Global Memory Map
Offset Channel/Register Name Access Reset Value
0x00 TC Channel 0 See Table 31-4
0x40 TC Channel 1 See Table 31-4
0x80 TC Channel 2 See Table 31-4
0xC0 TC Block Control Register BCR Write-only –
0xC4 TC Block Mode Register BMR Read/Write 0
Table 31-4. TC Channel Memory Map
Offset Register Name Access Reset Value
0x00 Channel Control Register CCR Write-only –
0x04 Channel Mode Register CMR Read/Write 0
0x08 Reserved –
0x0C Reserved –
0x10 Counter Value CV Read-only 0
0x14 Register A RA Read/Write
(1)
0
0x18 Register B RB Read/Write
(1)
0
0x1C Register C RC Read/Write 0
0x20 Status Register SR Read-only 0
0x24 Interrupt Enable Register IER Write-only –
0x28 Interrupt Disable Register IDR Write-only –
0x2C Interrupt Mask Register IMR Read-only 0
32058K
AVR32-01/12