Datasheet

64
AT32UC3A
It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pul-
lup, and does not need to be driven externally when negated. Table 13-4 lists these and other
reset sources supported by the Reset Controller.
Figure 13-6. Reset Controller block diagram
In addition to the listed reset types, the JTAG can keep parts of the device statically reset
through the JTAG Reset Register. See JTAG documentation for details.
Table 13-3. Reset description
When a Reset occurs, some parts of the chip are not necessarily reset, depending on the reset
source. Only the Power On Reset (POR) will force a reset of the whole chip.
Reset source Description
Power-on Reset Supply voltage below the power-on reset detector threshold
voltage
External Reset RESET_N pin asserted
Brownout Reset Supply voltage below the brownout reset detector threshold
voltage
CPU Error Caused by an illegal CPU access to external memory while
in Supervisor mode
Watchdog Timer See watchdog timer documentation.
OCD See On-Chip Debug documentation
JTAG
Reset
Controller
RESET_N
Power-O n
Detector
OCD
W atchdog Reset
RC_RCAUSE
CPU, HSB,
PBA, PBB
OCD, RTC/W DT
Clock Generato
Brownout
Detector
32058K
AVR32-01/12